IP175DLF datasheet(53/145 Pages) ETC

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IP175DLF

Datasheet

53/145

August 22, 2014

IP175DLF-DS-R10.1

number or a range port number. If the source’s logical port or the destination’s logical port in the incoming

packet match any of the pre-defined logical ports, the incoming frame will be discarded.

3.12.4

Layer 2-4 Multi-Field Filtering

IP175DLF support discard packets based on a combination of layer 2-4 Multi-Field packet headers.

3.13 IEEE 802.1x

IP175DLF support IEEE 802.1x security. The EAPOL is used by authentication process. EAPOL is

detected by checking destination MAC address defined in 01:80:C2:00:00:03 and then trap to CPU for

further processing. Eventually, CPU determines whether the port configures in authorized state or not.

CPU can also determine whether the requestor is qualified or not based on source MAC address. When

the switch is a VLAN-aware switch, CPU can determine whether the port (or SMAC) is placed in the

authorized state per VLAN.

3.14

Spanning Tree

In IP175DLF spanning tree operation separate into software implement and hardware implement. In

software implement CPU must process BPDU packet and configure the sate of each port. In hardware

implement the switch trap BPDU to CPU. The following table describes how to configure the state of each

port in IP175DLF.

State

Fwd BPDU

packet to CPU

Fwd BPDU packet

from CPU

Address

learning

Fwd all packet

normally

(Forward enable,

Learning enable)

Disable

X (note 2)

(0,0)

Blocking

X (note 3)

(0,0)

Listening

(0,0)

Learning

(0,1)

Forwarding

(1,1)

Note1: O: enabled, X: disabled

Note2: CPU should not send packets to IP175DLF and should discard packets from IP175DLF.

Note3: CPU should not send packets to IP175DLF.

Table 6 Configuring port state

IP175DLF Support fast aging function for RSTP, User can configure the parameter from MII register

20.14[6:5] and 20.14[4:0].

IP175DLF support 4 multiple spanning tree VLAN table which contains the VLAN-dependent port state.

MSTP allows users to map many VLANs to a spanning tree group, each with its own topology.

3.15

Special Tag

The purpose of special tag is:

To allow a frame (IP175DLF to CPU) to carrier ingress port number and violation event.

To allow a frame (CPU to switch) to indicate the output port mask and output queue number carrier

in special tag header

The VLAN TPID is represented in two octets, the hexadecimal value 8100. The octets display from left to

right, the left octet is 0x80 and the right octet is 0x00. Special tag information appears in the right octet

whose value is not a zero.

8 The forwarding and learning ability of each port are configured in MII register 20.6. For MSTP the

forwarding and learning ability of each port are configured in MII register 24.0-3.

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