IP175DLF datasheet(98/145 Pages) ETC

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IP175DLF

Datasheet

98/145

August 22, 2014

IP175DLF-DS-R10.1

5.4.3

MII1 MAC Mode or MII2 MAC Mode Register

(Only one is active at the same time.)

PHY

MII

ROM

R/W

Description

Default

2[15]

MAC_XCTRLEN[1]

Flow control capability of the link partner of external PHY on MII1

MAC or MII2 MAC

1: link partner supports flow control,

0: link partner does not support flow control

1’b1

2[14]

MAC_FORCE[1]

1: MII1orMII2’s speed and duplex are forced because

IP175DLF finds external PHY doesn’t support SMI

0: MII1orMII2 polls external PHY through SMI to decide its

speed and duplex.

1’b0

2[13]

MII1ORMII2 _LINK (MII1_LINK)

1: link ok, 0: un-link

1’b1

2[12:8]

42[4:0]

R/W Capability of external PHY on MII1 MAC or MII2 MAC

bit 12:

flow control ability,

bit 11:

100M full duplex,

bit 10 :

100M half duplex,

bit 9 :

10M full duplex,

bit 8:

10M half duplex

5’b

11111

2[7]

Speed of external PHY on MII1 MAC or MII2 MAC

1: 10M,

0: 100M

1’b0

2[6]

Duplex of external PHY on MII1 MAC or MII2 MAC

1: full duplex,

0: half duplex

1’b1

2[5]

Link status of external PHY on MII1 MAC or MII2 MAC

1: link on,

0: link off

1’b1

2[4:0]

43[4:0]

R/W MII1orMII2_MAC_PHY_ADDR[4:0]

5’b

00001

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