IP175DLF datasheet(3/145 Pages) ETC

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IP175DLF

Datasheet

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August 22, 2014

IP175DLF-DS-R10.1

4.3.2

MII Register 0 of PHY5 ......................................................................................... 62

4.4

MII Register 1 ..................................................................................................................... 63

4.4.1

MII Register 1 of PHY0~4 ..................................................................................... 63

4.4.2

MII Register 1 of PHY5 ......................................................................................... 65

4.5

MII Register 2 of PHY0~4 (5 PHYs share the MII register) ............................................... 66

4.6

MII Register 3 of PHY0~4 (5 PHYs share the MII register) ............................................... 66

4.7

MII Register 4 ..................................................................................................................... 67

4.7.1

MII Register 4 of PHY0~4 ..................................................................................... 67

4.7.2

MII Register 4 of PHY5 ......................................................................................... 69

4.8

MII Register 5 ..................................................................................................................... 70

4.8.1

MII Register 5 of PHY0~4 ..................................................................................... 70

4.8.2

MII Register 5 of PHY5 ......................................................................................... 71

4.9

MII Register 6 of PHY0~4 .................................................................................................. 72

4.10

MII Register 16 of PHY0~4 (5 PHYs share the MII register) ............................................. 72

4.11

MII Register 18 of PHY0~4 ................................................................................................ 72

4.12

MII Register 22 of PHY0~4 (5 PHYs share the MII register) ............................................. 73

Switch Register ............................................................................................................................. 74

5.1

Switch Register Map .......................................................................................................... 74

5.2

Switch Register EEPROM Map.......................................................................................... 78

5.3

Switch Control Register...................................................................................................... 79

5.3.1

Chip Identification.................................................................................................. 79

5.3.2

Software Reset Register ....................................................................................... 79

5.3.3

MII Force Mode ..................................................................................................... 80

5.3.4

Congestion Control Register ................................................................................. 80

5.3.5

Port State............................................................................................................... 82

5.3.6

Illegal Frame Filter ................................................................................................ 82

5.3.7

Special Packet Identification ................................................................................. 83

5.3.7.1

Reserved Address 01-80-C2-00-00-00 to 01-80-C2-00-00-1F ................... 83

5.3.7.2

Reserved Address 01-80-C2-00-00-20 to 01-80-C2-00-00-FF ................... 86

5.3.7.3

Miscellaneous Special Packet Identification................................................ 86

5.3.8

Network Security ................................................................................................... 89

5.3.9

Learning Control Register ..................................................................................... 89

5.3.10

Aging Time Parameter .......................................................................................... 91

5.3.11

Broadcast Storm Protection .................................................................................. 92

5.3.12

Port Mirror ............................................................................................................. 93

5.3.13

Source Block Protection........................................................................................ 94

5.3.14

LED Control Register ............................................................................................ 95

5.4

External MII Control Register ............................................................................................. 96

5.4.1

External MII Status Report Register...................................................................... 96

5.4.2

MII0 MAC Mode Register...................................................................................... 97

5.4.3

MII1 MAC Mode or MII2 MAC Mode Register ...................................................... 98

5.4.4

MII0, MII1 and MII2 Control Register 1 ................................................................. 99

5.4.5

MII0, MII1 and MII2 Control Register 2 ............................................................... 101

5.5

IGMP Control Register ..................................................................................................... 101

5.5.1

Base Control Register ......................................................................................... 101

5.5.2

Router Port Timeout ............................................................................................ 102

5.5.3

IGMP Group Timeout .......................................................................................... 103

5.6

Rate Control ..................................................................................................................... 104

5.6.1

Basic Rate Setting Register ................................................................................ 104

5.6.2

Rate Setting Access Control Register ................................................................. 104

5.7

Address Table Access Register........................................................................................ 105

5.7.1

Command Register ............................................................................................. 105

5.7.2

Data Buffer Register (For Unicast MAC Address)............................................... 105

5.7.3

Data Buffer Register (For Multicast MAC Address) ............................................ 105

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