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IP175DLF Datasheet(PDF) 59 Page - List of Unclassifed Manufacturers

Part # IP175DLF
Description  5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)
PDF  145 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP175DLF Datasheet(HTML) 59 Page - List of Unclassifed Manufacturers

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IP175DLF
Datasheet
The application of SMI
IP175DLF
MAC 1
MDC0
MDIO0
MDC1
MDIO1
MDC
MDIO
MDC
MDIO
MAC 2
MDC
MDIO
PHY1
MDC
MDIO
PHY2
Only one MAC is allowed to access the MDC0,MDIO0.
All PHY can be accessed via the MDC1,MDIO1.
3.20
Reset
The IP175DLF supports three kinds of reset function.
1. Hardware Reset: Pin 93 RESETB should be asserted LOW at least for 5ms to reset IP175DLF.
The IP175DLF gets initial values from pins and EEPROM after reset.
2. Software Reset: After Hardware Reset, user can write 16’h175D to PHY 20 Register 2 via SMI to reset
IP175DLF.The IP175DLF resets all of PHY’s and switch Engine, but IP175DLF does not load initial values
form pins and EEPROM.
3. PHY Reset: Please write “1” to bit 15 of MII register 0 to reset the PHY. The PHY address is from 0 to 4
for port 0~4 respectively.
3.21
Built in regulator
IP175DLF is built in one linear regulator.
It use pin 120 REG_OUT to control an external transistor to
generator a stable voltage source.
IP175DLF generates a voltage source between 1.85v ~ 2.05v.
4
PHY Register
4.1
PHY ID Map
PHY ID
Description
Default
Note
0
Port 0 PHY
1
Port 1 PHY
2
Port 2 PHY
3
Port 3 PHY
4
Port 4 PHY or MII1 PHY mode
5
TMII0/MII0/RMII0
6
MII2 PHY mode
20~27
Switch Registers
59/145
August 22, 2014
Copyright © 2007, IC Plus Corp.
IP175DLF-DS-R10.1



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