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IP175DLF Datasheet(PDF) 23 Page - List of Unclassifed Manufacturers

Part # IP175DLF
Description  5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)
PDF  145 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP175DLF Datasheet(HTML) 23 Page - List of Unclassifed Manufacturers

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IP175DLF
Datasheet
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August 22, 2014
Copyright © 2007, IC Plus Corp.
IP175DLF-DS-R10.1
Pin description (continued)
Pin No.
Label
Type
Description
External MII1 interface (MAC mode, MII1_PHY_MOD=0, P4EXT=1)
62
MII1_TXCLK
I
MII Transmit clock
It is an input clock and it is connected to MII_TXCLK of external
PHY
61,
60,
59, 58
TXD1_0,TXD1_1,
TXD1_2, TXD1_3
O
MII transmit data
It is connected to MII_TXD of external PHY. It is sent out at the
rising edge of MII1_TXCLK
57
TXEN1
O
MII transmit enable
It is an output signal and is connected to MII_TXEN of external
PHY. It is sent out at the rising edge of MII1_TXCLK.
69
COL1
I
MII collision
It is an input signal and is connected to the MII_COL of external
PHY.
63
RXDV1
I
MII receive data valid
It is an input signal and is connected to the MII_RXDV of
external PHY. RXDV1 is used to frame RXD1[3:0]
67,
66,
65, 64
RXD1_0, RXD1_1,
RXD1_2, RXD1_3
I
MII receive data
It is NRZ data and is connected MII_RXD[3:0] of external PHY. It
is received at the rising edge of MII1_RXCLK
68
MII1_RXCLK
I
MII receive clock



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