IP175DLF datasheet(51/145 Pages) ETC

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IP175DLF

Datasheet

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August 22, 2014

IP175DLF-DS-R10.1

2’b00: reserved

2’b01: discard frame if frame’s SMAC match MAC

address

2’b10: ignore VLAN member set

2’b11: copy frame to mirror port if frame’s DMAC match

MAC address

21.18[13:10]

PRI_INFO

Priority information: To assign queue number for frames with

match MAC table entry. The information is divided two parts:

match condition and its action.

Match Condition (21.18[13:12]):

2’b00: reserved

2’b01: match DMAC (Destination MAC Address)

2’b10: match SMAC (Source MAC Address)

2’b11: match DMAC or SMAC

Action (21.18[11:10]):

Assign to Queue 0

Assign to Queue 1

Assign to Queue 2

Assign to Queue 3

21.18[9:6]

FID

4-bit FID

21.18[5:0]

PORT_MAP

Port Map:

0x00: discard frame if frame’s DMAC match MAC

address

0x01 to 0x3F: destination port map

21.19.0

IGMP

IGMP entry indicator: This bit shall set to one

21.19.1

Valid

Entry is valid

Table 5 Entry content for IP multicast address

3.9.2

Accessing MAC Table

The MAC table can be accessed by through MII register 21.14-19. IP175DLF provides two access

commands: single read and single write. A single read or write transfer only executes a single I/O

operation and user only can access a particular memory address. When a given MAC+FID read from (or

write to) MAC table, the MAC+FID is used to compute hash index for mapping to MAC table.

Single Read

The single read process is described as following steps:

Step 1 – Set hash index in reg 21.14[10:0]

Step 2 – Set single read command in reg 21.14[12:11]

Step 3 – Set START bit in reg 21.14.15 to initiate read command

Step 4 – check DATA_VALID bit in reg 21.14.13 to determine if data is valid. If this bit is set to high, enter

to step 5

Step 5 – read data from data buffer register (reg 21.15-19). User must read data buffer register from reg

21.15 to reg 21.19 in regular order.

Single Write

The single write process is described as following steps:

Step 1 – Write desired data to data buffer register (reg 21.15-19)

Step 2 – Set hash index in reg 21.14[10:0]

Step 3 – Set single write command in reg 21.14[12:11]

Step 4 – Set START bit in reg 21.14.15 to initiate read command

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