IP175DLF datasheet(97/145 Pages) ETC

Part #	IP175DLF

Description	5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)

PDF	145 Pages

Scroll/Zoom	100%

Manufacturer	ETC [List of Unclassifed Manufacturers]

Direct Link

Logo

97 / 145 page

IP175DLF

Datasheet

97/145

August 22, 2014

IP175DLF-DS-R10.1

5.4.2

MII0 MAC Mode Register

PHY

MII

ROM

R/W

Description

Default

1[15]

MAC_XCTRLEN[0]

Flow control capability of the link partner of external PHY on

MII0

1: link partner supports flow control,

0: link partner does not support flow control

1’b1

1[14]

MAC_FORCE[0]

1: MII0’s speed and duplex are forced because IP175DLF finds

external PHY doesn’t support SMI

0: MII0 polls external PHY through SMI to decide its speed and

duplex.

1’b0

1[13]

MII0_link

1: link ok, 0: un-link

1’b1

1[12:8]

40[4:0]

R/W Capability of external PHY on MII0

bit12: flow control ability,

bit11: 100M full duplex,

bit10 : 100M half duplex,

bit9 : 10M full duplex,

bit8: 10M half duplex

5’b

11111

1[7]

Speed of external PHY on MII0

1: 10M,

0: 100M

1’b0

1[6]

Duplex of external PHY on MII0

1: full duplex,

0: half duplex

1’b1

1[5]

Link status of external PHY on MII0

1: link on,

0: link off

1’b1

1[4:0]

41[4:0]

R/W MII0_MAC_PHY_ADDR[4:0]

5’b

00000

IP175DLF Datasheet(PDF) 97 Page - List of Unclassifed Manufacturers

IP175DLF Datasheet(HTML) 97 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL