IP175DLF datasheet(4/145 Pages) ETC

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IP175DLF

Datasheet

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August 22, 2014

IP175DLF-DS-R10.1

5.7.4

Data Buffer Register (For IP Multicast Address) ................................................. 106

5.8

CPU Interrupt Register ..................................................................................................... 107

5.8.1

CPU Interrupt Control Register ........................................................................... 107

5.8.2

Loop detection enable Register .......................................................................... 107

5.8.3

Loop port indicator Register ................................................................................ 107

5.9

Miscellaneous Control Register ....................................................................................... 108

5.10

CRC Counter.................................................................................................................... 110

5.11

VLAN Group Control Register.......................................................................................... 110

5.11.1

VLAN Classification............................................................................................. 110

5.11.2

VLAN Ingress Rule.............................................................................................. 112

5.11.3

VLAN Egress Rule .............................................................................................. 112

5.11.4

Default VLAN Information ................................................................................... 113

5.11.5

VLAN Table ......................................................................................................... 114

5.11.5.1

VLAN Control Register ...............................................................................114

5.11.5.2

VLAN Identifier Register.............................................................................114

5.11.5.3

VLAN Member Register .............................................................................115

5.11.5.4

Add Tag Control Register ...........................................................................117

5.11.5.5

Remove Tag Control Register ....................................................................118

5.11.5.6

VLAN Miscellaneous Register................................................................... 120

5.11.5.7

Spanning Tree Table.................................................................................. 121

5.12

Quality of Service (QOS).................................................................................................. 122

5.12.1

Priority Classification........................................................................................... 122

5.12.1.1

Base Control Register ............................................................................... 122

5.12.1.2

Port Priority Map........................................................................................ 122

5.12.1.3

VLAN Priority Map ..................................................................................... 123

5.12.1.4

TOS/DSCP Priority Map ............................................................................ 124

5.12.1.5

TCP/UDP Port Priority ............................................................................... 127

5.12.2

Queue Scheduling Configuration Register.......................................................... 128

5.13

QoS Multi-Field Classification .......................................................................................... 130

5.13.1

Multi-Field Classification Table Control Register................................................. 130

5.13.2

Multi-Field Classification Register ....................................................................... 131

5.13.3

Multi-Field Table QoS Rate Control Register ...................................................... 133

5.13.4

Multi-Field Access Control Register .................................................................... 133

5.13.5

Multi-Field Status Register .................................................................................. 134

5.14

Auto Blocking/Recovery loop port .................................................................................... 134

Crystal Specifications .................................................................................................................. 135

Electrical Characteristics............................................................................................................. 136

7.1

Absolute Maximum Rating ............................................................................................... 136

7.2

DC Characteristic ............................................................................................................. 136

7.3

AC Timing......................................................................................................................... 137

7.3.1

Power On Sequence and Reset Timing.............................................................. 137

7.3.2

PHY Mode MII (Turbo MII) Timing....................................................................... 138

7.3.3

MAC Mode MII (Turbo MII) Timing...................................................................... 139

7.3.4

RMII Timing ......................................................................................................... 140

7.3.5

SNI Timing........................................................................................................... 141

7.3.6

SMI Timing .......................................................................................................... 142

7.3.7

EEPROM Timing ................................................................................................. 144

7.4

Thermal Data.................................................................................................................... 144

Order Information ........................................................................................................................ 144

Package Detail ............................................................................................................................ 145

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