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IP175DLF Datasheet(PDF) 40 Page - List of Unclassifed Manufacturers |
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IP175DLF Datasheet(HTML) 40 Page - List of Unclassifed Manufacturers |
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40 / 145 page  IP175DLF Datasheet 40/145 August 22, 2014 Copyright © 2007, IC Plus Corp. IP175DLF-DS-R10.1 Abbreviation: I/F: the type of interface Mode: the port works as a MAC or a PHY Int: the internal block to which the MII port is connected MAC4: the port 4 of switch engine MAC5: the port 5 of switch engine PHY4: the port 4 of PHY 3.4.1 To define the speed, duplex and pause of MII port MII interface can be configured as either MAC mode or PHY mode. In MAC mode and PHY mode, the MII port’s speed, duplex and pause ability can set through pin, EEPROM or MII register. In MAC mode it can also use polling PHY status to get PHY link capability. Therefore IP175DLF provide MDC1/MDIO1 for polling PHY status. The details are shown in the following tables. MII0 PHY mode EEPROM MII register Pin Name Reg Name Phy Reg MII0 speed MAC5_F_100 MAC5_FORCE_100 2.7 MAC5_FORCE_100 20 4.15 MII0 duplex MAC5_F_FULL MAC5_FORCE_FULL 2.5 MAC5_FORCE_FULL 20 4.13 MII0 pause -- MAC_X_EN 3.0 MAC_X_EN 20 5.0 MII0 MAC mode: There are two ways to set MII0 speed, duplex and pause. 1. Decided by reading the MII registers 0~5 of external PHY through MDC1, MDIO1. MII0 Speed Duplex Pause 1. IP175DLF polls the external PHY with address defined in MII register 21.1[4:0]. The default address value is 00000. 2. After reset, IP175DLF writes the speed/duplex/pause capability to the external PHY using the content of MII register 21.1[12:8]. 3. IP175DLF reads MII register 0~5 of external PHY as MII0 speed, duplex and pause continuously. 2. Force mode (MDC1 and MDIO1 are not connected to external PHY) EEPROM MII register Pin Name Reg Name Phy Reg MII0 speed MAC5_F_100 MAC5_FORCE_100 2.7 MAC5_FORCE_100 20 4.15 MII0 duplex MAC5_F_FULL MAC5_FORCE_FULL 2.5 MAC5_FORCE_FULL 20 4.13 MII0 pause -- MAC_X_EN 3.0 MAC_X_EN 20 5.0 |
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