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IP175DLF Datasheet(PDF) 79 Page - List of Unclassifed Manufacturers

Part # IP175DLF
Description  5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)
PDF  145 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP175DLF Datasheet(HTML) 79 Page - List of Unclassifed Manufacturers

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IP175DLF
Datasheet
79/145
August 22, 2014
Copyright © 2007, IC Plus Corp.
IP175DLF-DS-R10.1
5.3
Switch Control Register
R/W = Read/Write, SC = Self-Clearing, RO = Read Only
5.3.1
Chip Identification
PHY
MII
ROM
R/W
Description
Default
20
0[15:0]
--
RO
PART_NUM
Part ID number
16’h
175D
5.3.2
Software Reset Register
PHY
MII
ROM
R/W
Description
Default
2[15:0]
--
R/W SOFT_RESET[15:0]
Software reset register
IP175DLF is reset if uses write “175D” to this register. It is
self-cleared. The reset period is around 2ms. User has to wait
for at least 2 ms to access IP175DLF.
When read this register, it shows the internal status of
IP175DLF.
16’h00
20
3[1:0]
--
R/W TABLE_LOCK[1:0]
Lock content of table.
Bit[1]: Multi-Field table
Bit[0]: Address table
2’b00



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