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DA6021 Datasheet(PDF) 161 Page - Renesas Technology Corp |
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DA6021 Datasheet(HTML) 161 Page - Renesas Technology Corp |
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161 / 225 page  DA6021 HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Company Confidential Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 161 of 224 www.dialog-semiconductor.com Figure 67: BCU Warning Flag Generation There is a possibility to disable and change the polarity of a certain output via BEH register setting. In addition it is possible to have a sticky output so under certain conditions an output is asserted, the output value is maintained even when the condition is not valid.. The sticky function is selected with the ST bit and is cleared with the CL bit. The CL bit must be a self-clearing bit. Register Name BCUIRQ Address 0x07 Page 1 Read/Write Reset Value 0x00 MSB LSB R R R R R R/W R/W R/W reserved VCRIT VWARNB VWARNB VWARNB 0 1 No interrupt pending Interrupt pending VWARNA 0 1 No interrupt pending Interrupt pending VCRIT 0 1 No interrupt pending Interrupt pending Register Name MBCUIRQ Address 0x14 Page 1 Read/Write Reset Value 0x07 MSB LSB R R R R R R/W R/W R/W reserved MVCRIT MVWARNB MVWARNB MVWARNB 0 1 Interrupt not masked Interrupt masked MVWARNA 0 1 Interrupt not masked Interrupt masked MVCRIT 0 1 Interrupt not masked Interrupt masked Prog. Trip Point VSYS VWARNA setting Prog. Debounce VWARNA_FLAG VSYS VWARNB setting UNDER_VWARNA VSYS VCRIT setting Prog. Debounce VWARNB_FLAG UNDER_VWARNB Prog. Debounce VCRIT_FLAG UNDER_VCRIT Prog. Trip Point Prog. Trip Point VWARNA[2:0] VWARNA_DB[3:0] VWARNB[2:0] VWARNB_DB[3:0] VCRIT[2:0] VCRIT_DB[2:0] VWARNA_EN VWARNB_EN Master VWARNB Circuit Enable Master VWARNA Circuit Enable Master VCRIT Circuit Enable VCRIT_EN |
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