DA6021 datasheet(179/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

179 of 224

www.dialog-semiconductor.com

17. General Purpose IOs

Overview

17.1

DA6021 provides 16 GPIO pins for general purpose IOs under the control of the SoC. The majority of these

GPIO pins have a default configuration as CMOS inputs with weak (50 KOhm) pull downs enabled. The GPIO

buffers support operation as open-drain or push pull outputs. They are split into 2 groups, each with a different

fixed supply:



GPIO0P0

– GPIO0P7 support a level of 1.8V



GPIO1P0

– GPIO1P7 support 3.3V

Following are the supported feature from the digital GPIO IP:



CMOS or Open Drain output and input configuration



2k-ohm or 50k-ohm pull-up or pull-down resistance



Read back of output PAD values



Output Level select by register



Digital glitch filter of 62µs



Digital filter (de-bouncer, typically 32ms) with programmable bypass



Interrupt and interrupt mask functionality.



Polarity selection (default active high)



Analog/Digital Input



Alternate input/output functionality.

Note: for the implementation of the GPIO core functionality is useful to know that the register file will not be part

of the IP, same is for the logic which controls the mapping of the alternate functions.

Analog Block, Control & Data Signals

17.2

Figure 69 : GPIO Block Diagram

As is shown from the above picture (analog block as black box) there are 5 signals which controls the analog

behavior of the GPIO pin. Note that EN is generated from the analog pad block itself.

The following tables show the coding for configuring the GPIO pads.

GPIO

ANALOG

DIR [1:0]

PULL[EN, DIR, LVL]

DOUT

PAD

DIN

To ANA

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