DA6021 datasheet(190/225 Pages) RENESAS

190 / 225 page

DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

190 of 224

www.dialog-semiconductor.com

19. Interrupt Controller

Overview

19.1

The interrupt control unit maintains the state of the First Level IRQ tree and is responsible for asserting and de-

asserting the DA6021’s IRQ to the application SoC. It contains status bits for interrupts from all the second-level

sub-blocks. If unmasked, the second-level interrupts will propagate to the appropriate first-level interrupt bit, as

assigned below. If the first-level interrupt is unmasked, it will propagate to the IRQ pin, which will remain high as

long as unmasked interrupts have not been cleared.

First Level Interrupt

19.2

DA6021 interrupt signal IRQ signal is connected to a GPIO of the SoC indicating DA6021 unmasked events to

be investigated by the SOC while reading the IRQ status registers via I2C.

The DA6021 interrupt scheme contains two levels. The first-level interrupt register contains 6 IRQ bits, and

indicates which PMIC sub-block triggered the interrupt. One bit is dedicated to each of the interrupt-causing

DA6021 sub-blocks. For all units, the second-level interrupt registers indicate the specific interrupt triggers for

each sub-block. A masking system is provided to enable or disable specific interrupt handlers.

If any bits are set in the first-level IRQ mask, the assertion of an interrupt from the masked sub-block(s) will not

cause an assertion of the IRQ signal, nor will it set the first-level IRQ bit. By limiting the first-level IRQ bits set to

only those that are unmasked; this disambiguates the dispatching of interrupts.

First-Level IRQ bits may not be directly cleared; they are cleared by clearing all unmasked second-level IRQ bits,

and then are implicitly cleared.

When all unmasked first-level IRQ bits are implicitly cleared (all unmasked second-level interrupts directly

cleared), the IRQ pin is de-asserted.

Figure 70: 1st Level Interrupts

Second Level Interrupt

19.3

While First-Level Interrupt bits inform the interrupt handler of which sub-block interrupted, second-level interrupt

egisters/bits provide the interrupt handler with the specific nature of the block‘s interrupt event.

If any bits are set in a second-level interrupt mask, then the appropriate second level interrupt bit is prevented

from asserting the first level interrupt bit for the corresponding sub-block, nor will the bit become set. (Only

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