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DA6021 Datasheet(PDF) 191 Page - Renesas Technology Corp |
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DA6021 Datasheet(HTML) 191 Page - Renesas Technology Corp |
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191 / 225 page  DA6021 HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Company Confidential Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 191 of 224 www.dialog-semiconductor.com Interrupt bits are write-1-to-clear. This includes all second-level interrupt register locations. The IRQ signal will not be de-asserted until all unmasked interrupt bits are cleared. For detailed description of Second level interrupts refer to the dedicated blocks in this document. The table below summarizes the second level interrupts. Interrupt Name Register Source First-Level Interrupt Related Status Bit DESCRIPTION VBUSDET PWRSRCIRQ Input Power source Detection PWRSRC SVBUSDET Indicates that a valid VBUS voltage is detected or removed. Software can test the current cable connection status by checking the SVBUSDET bit in SPWRSRC. DCINDET PWRSRCIRQ Input Power source Detection PWRSRC SDCINDET Triggered when a AC/DC adapter has been detected or removed. The status of the DC cable connection can be verified by reading the SDCINDET bit in SPWRSRC. BATDET PWRSRCIRQ Input Power source Detection PWRSRC SBATDET Interrupt is triggered when a battery is connected or disconnected. The status of the battery connection can be verified by reading the SBATDET bit in SPWRSRC. SYS0ALRT0 THRMIRQ0 Thermal Control Unit THRM Set by the thermal state machine when a system thermistor 0 temperature thermal alert0 occurs SYS1ALRT0 THRMIRQ0 Thermal Control Unit THRM Set by the thermal state machine when a system thermistor 1 temperature alert0 occurs SYS2ALRT0 THRMIRQ0 Thermal Control Unit THRM Set by the thermal state machine when a system thermistor 2 temperature alert0 occurs PMICALRT0 THRMIRQ0 Thermal Control Unit THRM Set by the thermal state machine when a PMIC die temperature alert0 occurs SYS0ALRT1 THRMIRQ0 Thermal Control Unit THRM Set by the thermal state machine when a system thermistor 0 temperature alert1 occurs SYS1ALRT1 THRMIRQ0 Thermal Control Unit THRM Set by the thermal state machine when a system thermistor 1 temperature alert1 occurs SYS2ALRT1 THRMIRQ0 Thermal Control Unit THRM Set by the thermal state machine when a system thermistor 2 temperature alert1 occurs PMICALRT1 THRMIRQ0 Thermal Control Unit THRM Set by the thermal state machine when a PMIC die temperature alert1 occurs SYS0CRIT THRMIRQ1 Thermal Control Unit THRM Set by the thermal state machine when a system thermistor 0 critical temperature event occurs SYS1CRIT THRMIRQ1 Thermal Control Unit THRM Set by the thermal state machine when a system thermistor 1 critical temperature event occurs SYS2CRIT THRMIRQ1 Thermal Control Unit THRM Set by the thermal state machine when a system thermistor 2 critical temperature event occurs PMICCRIT THRMIRQ1 Thermal Control THRM Set by the thermal state machine when a PMIC die critical temperature event |
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