DA6021 datasheet(193/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

193 of 224

www.dialog-semiconductor.com

Interrupt Name Register

Source

First-Level

Interrupt

Status Bit

DESCRIPTION

for rise, fall or both. See GPIOxPxCTLI

registers for INTCNTxPx setting.

Triggered when the conditions set with

GPIOxPxCTLI registers have been met.

The status of the GPIO input can be

verified by reading the DINxPx bit from

the GPIOxPxCTLI register.

VHDMIOCP

VHDMIIRQ

VHDMI

VHDMIOCP

Bit is set when VHDMI over current

condition occurs if not masked

Table 110: Second Level Interrupts

Critical Race Condition (set vs. clear)

19.4

An IRQ register can only be cleared by the SoC. This can lead to a potential for critical race if a certain block try

to assert the interrupt and at the same time the clearing command comes from the SoC. In this case it is given

priority to the block skipping the clearing. In this case the SoC will try to clear it again. Due to block running with

lower frequency (lowest 31,25 KHz) some of the IRQ can be in the SET mode for a time window of circa 30us.

This means that the IRQ, in the corner case when clear is concurrent, it cannot be cleared within that time

window.

Interrupt Controller Registers

19.5

IRQLVL1

Address

0x02

Page 1

Read

Reset Value 0x00

MSB

LSB

reserved

HDMI

GPIO

CHRG

ADC

BCU

THRM

PSDL

PSDL IRQ not asserted

PSDL IRQ asserted

THRM

THRM IRQ not asserted

THRM IRQ asserted

BCU

BCU IRQ not asserted

BCU IRQ asserted

ADC

ADC IRQ not asserted

ADC IRQ asserted

CHRG

CHRG IRQ not asserted

CHRG IRQ asserted

GPIO

GPIO IRQ not asserted

GPIO IRQ asserted

HDMI

HDMI IRQ not asserted

HDMI IRQ asserted

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