DA6021 datasheet(196/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

196 of 224

www.dialog-semiconductor.com

Power Button

20.4

The DA6021 PWRBTNIN_B input pin has an internal pull-

up resistor (20kΩ ± 10%) to VSYS and includes a

30ms de-bouncing filter of 30ms, ensuring that spurious transitions are not logged. The de-bounced signal is

forwarded to the timer logic, measuring the pulse length and comparing it with pre-programmed timing registers.

DA6021 passes such power button information level-shifted to the SOC via the PWRBTN_B output pin. Such

PWRBTN_B signal is only valid when RSMRST=1.

If the system is in SOC_G3 state and the power button is pressed more than 100ms, the DA6021 switches on all

suspend (*_A) rails, de-asserts RSMRST_B after the power button is released and passes the power button

information towards the SoC.

If the system is active or down to SOC_S4, pressing the power button will cause DA6021 to pass the level

shifted PWRBTNIN_B signal after 100ms de-bouncing to the SoC, which takes the appropriate actions.

Power Button Cold Boot Flow Diagram

20.5

The chart below shows how the boot signal is generated from the power button.

Figure 72: Power Button Boot Flow Diagram

SOC G3

Power Button

Pressed

HT Timer Starts

After

Debouncing

PB Still Held

PMIC Starts Cold Boot

by Turning on SUS

Rails, RSMRST_B=1

Power Button

Released

PBHT Timer

Stops

(Maximum

15.5s)

PMIC Clears

PBHT Timer.

Yes

SOC S4

PMIC Passes PWRBTN_B

to SOC and Takes

SLP_S*_B Signals from

SOC to Complete Cold

Boot , SOC Asserts

PLTRST_B

SOC S0

DA6021 Datasheet(PDF) 196 Page - Renesas Technology Corp

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