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DA6021 Datasheet(PDF) 197 Page - Renesas Technology Corp |
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DA6021 Datasheet(HTML) 197 Page - Renesas Technology Corp |
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197 / 225 page  DA6021 HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Company Confidential Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 197 of 224 www.dialog-semiconductor.com Force a Cold Off Sequence 20.6 DA6021 triggers a “Cold Off” sequence when the power button is hold for more than in register PBCONFIG specified time (default is 4sec). In the event of such a “Cold Off” sequence, DA6021 sets the RFCO (Reset due to Forced Cold Off) in register RESETSRCCRIT and clears the timer PBHT bits in the power button status register PBSTATUS. The PMIC shuts down the system by turning off all its voltage rails in sequence without waiting for instructions (e.g. SLP_S*_B signals) from the SOC. Force Cold Off Flow Diagram 20.7 Figure 73: Power Button Cold Off Flow Diagram UIBTN_B 20.8 The UIBTN_B pin is an input from a platform-defined functional interface button, such as the Home button. The GPIO1P0 pin can be programmed with its alternate function for the UI button. It is internally connected to VSYS via a pull-up resistor (20KOhm±10%). It includes a 30ms de- bouncer to ensure that spurious transitions aren’t logged while the switch contacts bounce on initial contact. The output of the de-bouncer enters the edge detect circuits. Both edges can trigger a utility button interrupt, which is the GPIOP1P0 bit in the second-level GPIO0IRQ Register. It is cleared when a 1 is written to this location. The output of the de-bouncer can be read from the UIBLVL bit of the UIBSTATUS register to determine the current state of the button. SOC S0 Power Button Pressed HT Timer Starts After Debouncing PB Still Held PMIC Passes the Power Button Press Information to SOC via PWRBTN_B No Yes No Yes PMIC Takes SLP_S*_B Signals from SOC to Settle on an Appropriate PMIC Power State SOC S0IX/ S3/G3 PB Still Held, PBHT Timer >= FLCOT No Forced Cold Off: PMIC Turns off all VRs Sequentially without Waiting for SLP_S*_B from SOC SOC G3 Yes PMIC Sets RFCO Bit Power Button Released PBHT Timer Stops (Maximum 15.5s) PMIC Clears PBHT Timer. |
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