TMS320F datasheet(192/389 Pages) TI

192 / 389 page

LTA

Load TREG and Accumulate Previous Product

7-92

Syntax

LTA

dma

Direct addressing

LTA

ind [, ARn]

Indirect addressing

Operands

dma:

7 LSBs of the data-memory address

Value from 0 to 7 designating the next auxiliary register

ind:

Select one of the following seven options:

*–

*0+

*0–

*BR0+

*BR0–

LTA

dma

987

6543

210

dma

LTA

ind [, ARn]

987

6543

210

ARU

NAR

Note:

ARU, N, and NAR are defined in section 6.3,

Indirect Addressing Mode (page 6-9).

Execution

Increment PC, then ...

(data-memory address)

→ TREG

(ACC) + shifted (PREG)

→ ACC

Status Bits

Affected by

Affects

PM and OVM

C and OV

Description

TREG is loaded with the contents of the specified data-memory address. The

contents of the product register, shifted as defined by the PM status bits, are

added to the accumulator, and the result is placed in the accumulator.

The carry bit is set (C = 1) if the result of the addition generates a carry and

is cleared (C = 0) if it does not generate a carry.

The function of the LTA instruction is a subtask of the LTD instruction.

Words

Cycles for a Single LTA Instruction

Program

Operand

ROM

DARAM

SARAM

External

DARAM

1+p

SARAM

1, 2†

1+p

External

1+d

2+d+p

† If the operand and the code are in the same SARAM block

Opcode

Cycles

TMS320F Datasheet(PDF) 192 Page - Texas Instruments

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