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TMS320F Datasheet(PDF) 260 Page - Texas Instruments

Part # TMS320F
Description  CPU and Instruction Set
PDF  389 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F Datasheet(HTML) 260 Page - Texas Instruments

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SPH
Store High PREG
7-160
Syntax
SPH
dma
Direct addressing
SPH
ind [, ARn]
Indirect addressing
Operands
dma:
7 LSBs of the data-memory address
n:
Value from 0 to 7 designating the next auxiliary register
ind:
Select one of the following seven options:
*
*+
*–
*0+
*0–
*BR0+
*BR0–
SPH
dma
15
14
13
12
11
10
987
6543
210
1
0
0
0
1
1
0
1
0
dma
SPH
ind [, ARn]
15
14
13
12
11
10
987
6543
210
1
0
0
0
1
1
0
1
1
ARU
N
NAR
Note:
ARU, N, and NAR are defined in section 6.3,
Indirect Addressing Mode (page 6-9).
Execution
Increment PC, then ...
16 MSBs of shifted (PREG)
→ data-memory address
Status Bits
Affected by
PM
Description
The 16 high-order bits of the PREG, shifted as specified by the PM bits, are
stored in data memory. First, the 32-bit PREG value is copied into the product
shifter, where it is shifted as specified by the PM bits. If the right-shift-by-6
mode is selected, the high-order bits are sign extended and the low-order bits
are lost. If a left shift is selected, the high-order bits are lost and the low-order
bits are zero filled. If PM = 00, no shift occurs. Then the 16 MSBs of the shifted
value are stored in data memory. Neither the PREG value nor the accumulator
value is modified by this instruction.
Words
1
Cycles for a Single SPH Instruction
Program
Operand
ROM
DARAM
SARAM
External
DARAM
1
1
1
1+p
SARAM
1
1
1, 2†
1+p
External
2+d
2+d
2+d
4+d+p
† If the operand and the code are in the same SARAM block
Opcode
Cycles



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