AMD-762 datasheet(22/122 Pages) AMD

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Functional Operation

Chapter 2

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

2.2

Memory Interface

The AMD-762 memory controller arbitrates and optimizes

incoming memory requests, handles ECC and Graphics

Address Remapping Table (GART), and controls up to four

double-data-rate (DDR) SDRAM DIMMs.

The AMD-762 system controller memory interface is designed

to support registered DDR DIMMs. Up to four registered

DIMMs can be supported by the AMD-762 system controller.

The AMD-762 system controller supports 64-Mbit, 128-Mbit,

256-Mbit, and 512-Mbit DDR devices. Device widths of x4, x8,

and x16 are supported. Mixed banks are supported, meaning

that a x8 DIMM can coexist with x4 and x16, etc.

Refer to Table 1 on page 11 for the total memory sizes for

various registered DIMM configurations. A total of 4 Gbytes is

supported.

DDR timing parameters are programmable via the AMD-762

system controller’s memory controller configuration registers,

allowing support of different DIMM configurations and

loading. Refresh is also programmable, with support of various

refresh rates as well as the ability to queue up to four

outstanding refreshes. Clock pairs can also be selectively

disabled to unpopulated DIMM slots via configuration register

bits in the memory controller.

The memory controller supports up to four open pages in the

active chip select. All pages in a chip select are closed when an

access to another chip select is detected. Memory page

operation can be further optimized by programming the

n u mber of i d le c y c l es to a ba nk be f o re the bank is

automatically precharged.

AMD-762 Datasheet(PDF) 22 Page - Advanced Micro Devices