AMD-762 datasheet(65/122 Pages) AMD

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Chapter 4

Electrical Data

24416C—December 2001

AMD-762™ System Controller Data Sheet

Preliminary Information

4.4

Power Dissipation

Table 15 shows typical and maximum power dissipation of the

AMD-762 system controller during normal and reduced power

states. The measurements are taken with the VDD shown.

4.5

Switching Characteristics and Requirements

The AMD-762 system controller signal switching characteristics

and requirements are presented in Tables 16 through 27. All

signal timings are based on the following conditions:

The target signals are input or output signals that are

switching from logical 0 to 1, or from logical 1 to 0.

Measurements are taken from the time the reference signal

(AGPCLK, PCICLK, CLKOUT, SYSCLK, or RESET#) passes

through 1.5 V to the time the target signal passes through 1.5 V.

Parameters are within the range of those listed in

“Operating Ranges” on page 48.

4.5.1

Clock Switching Requirements

Table 16 contains the switching characteristics of the SYSCLK

input to the AMD-762 system controller for 100-MHz processor

bus operation. These timings are all measured with respect to

the voltage levels indicated by Figure 12 on page 54. Clock

skew requirements are shown in Figure 14 on page 56. Table 17

on page 55 contains the switching characteristics of the

AGPCLK input for 66-MHz PCI bus operation. Table 18 on

page 55 contains the switching characteristics of the PCICLK

input for 33-MHz PCI bus operation. These timings are all

Table 15.

Typical and Maximum Power Dissipation*

Supply

Normal Operation

Low-Power States

Typical

Maximum

ACPI S1 State

ACPI S3 State

VDD_CORE

100 MHz

133 MHz

3 W

4 W

4.5 W

6 W

125 mW

165 mW

50 mW

65 mW

*This table contains preliminary information, which is subject to change.

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