AMD-762 datasheet(74/122 Pages) AMD

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Electrical Data

Chapter 4

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

4.5.3

AGP/PCI Signals

Valid Delay, Float,

Setup, and Hold

Timings

The valid delay and float timings for output signals during

functional operation are relative to the rising edge of the given

clock. The maximum valid delay timings are provided to allow

a system designer to determine if setup times can be met.

Likewise, the minimum valid delay timings are used to analyze

hold times.

The setup and hold time requirements for the AMD-762 system

controller input signals presented here must be met by any

device that interfaces with it to assure the proper operation of

the AMD-762 system controller.

Figure 20 shows the relationship between the rising clock edge

and setup, hold, and valid data timings.

Figure 20.

Setup, Hold, and Valid Delay Timings

AGP Interface Timing

The 4x AGP interface of the AMD-762 system controller can

operate in three modes — 1x, 2x, and 4x, and complies to the

AGP specification parameters.

The timings for the 1x mode, shown in Table 22 on page 63, are

relative to AGPCLK. The timings for the 2x mode, shown in

Table 23 on page 64, are relative to the respective strobe.

The timings for the 4x mode, shown in Table 24 on page 65,

apply only to the inner loop 4x clock mode signals (AD, C/BE#,

and SBA).

Figure 21 on page 65 shows an AGP 2x strobe/data turnaround

timing diagram. Figure 22 on page 66 and Figure 23 on page 66

show AGP 2x and 4x timing diagrams, respectively. Figure 24

on page 67 shows an AGP 4x strobe/data turnaround timing

diagram.

tsu

tvd

Data In

Data Out

CLK

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