AMD-762 datasheet(38/122 Pages) AMD

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Functional Operation

Chapter 2

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

T h e pr oc es sor and the A M D-762 syst em contr o l l er

communicate power-state transitions through the AMD Athlon

system bus connect/disconnect protocol and special cycles

(masked writes to a defined AMD Athlon system bus address

with specific data encoding). In general, the processor initiates

a request for a disconnect with a special cycle, and the

AMD-762 system controller may or may not actually disconnect

the processor with the connect/disconnect protocol. The

AMD-7 62 system contro ll er perfor m s the re quested

connect/disconnect as part of the process of entering and

exiting certain ACPI states. The following two special cycles

are of interest:

Halt—Generated

the

AMD Athlon

processors

response to executing a HALT instruction. The AMD-762

system controller forwards the Halt special cycle to the PCI

bus but does not perform any further power management

for Halt conditions. The processor buses remain connected

and the memory is not placed in self-refresh mode.

Stop Grant—Generated by the AMD Athlon processors in

response to assertion of STPCLK#. When the AMD-762

system controller receives a Stop Grant from the processor,

it waits for a Stop Grant from the second processor (if

installed), then it sends a Stop Grant special cycle on the

PCI bus. The AMD-762 system controller initiates the

following sequence of actions if the Stop Grant disconnect

bit is set (Dev 0:F0:0x60):

A. Disables PCI/AGP arbitration and waits for all queues to

memory to be empty (including refresh requests).

B. Completes the AMD Athlon system bus cycles. The

AMD-762

system

controller

then

initiates

AMD Athlon system bus disconnect to the processors,

and causes the memory to enter self-refresh.

C. The Southbridge decodes the special cycle and enters the

appropriate power state. The Southbridge can then

assert DCSTOP#.

Halt special cycles are generally considered part of an ACPI

state definition (C1). STPCLK#, however, can be asserted at

random times while the processor is in the full-running state

(C0) to conserve power (clock throttling).

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