AMD-762 datasheet(15/122 Pages) AMD

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Chapter 1

Features

24416C—December 2001

AMD-762™ System Controller Data Sheet

Preliminary Information

BIOS-configurable

memory-timing

parameters

and

configuration parameters

2.5-V memory interface operation with no external buffers

or PLLs

Concurrent DRAM writeback and read-around-write

Burst read and write transactions

Decoupled and burst DRAM refresh with staggered CS

timing

Provides the following refresh options:

•

Programmable refresh rate

•

CAS-before-RAS

•

Populated banks only

•

Automatic refresh of idle slots—improves bus availability

for memory access by the processor or system

1.3

PCI Bus Controller

The PCI bus controller has the following features:

Compliance with PCI Local Bus Specification, Revision 2.2.

Supports up to seven PCI bus masters plus the AMD-766

peripheral bus controller when operating in 33-MHz-only mode,

or up to two PCI bus masters and the AMD-768 peripheral bus

controller when operating in 66/33-MHz PCI mode.

64-bit interface, compatible with 3.3-V and 5-V PCI I/O

Synchronous PCI bus operation up to 66 MHz

PCI-initiator peer concurrency

Automatic processor-to-PCI burst cycle detection

Zero wait-state PCI initiator and target burst transfers

Enhanced PCI command optimization, such as Memory

Read Line (MRL), Memory Read Multiple (MRM), and

Memory-Write-and-Invalidate (MWI)

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