AMD-762 datasheet(95/122 Pages) AMD

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Chapter 7

Signal Descriptions

24416C—December 2001

AMD-762™ System Controller Data Sheet

Preliminary Information

SCHECK[7:0]#

AMD Athlon™ Processor System Bus Data Bus Check Byte

SCHECK[7:0]# transfer ECC check bits for data transferred on the SDATA[63:0]# bus.

As Outputs:

The AMD-762™ system controller drives SCHECK[7:0]# with each valid data

quadword. SCHECK[7:0]# are skew-aligned with the source-synchronous clocks,

SDATAINCLK[3:0]#.

As Inputs:

The AMD-762 system controller samples SCHECK[7:0]# and transfers the data

to the memory. SCHECK[7:0]# are sampled by the AMD-762™ system controller on each

edge of SDATAOUTCLK[3:0]#.

SCHECK[7:0]# are floated by RESET#. Check bits for write data are driven by the processor

and check bits for read data are driven by the system controller. The AMD-762 system

controller drives the previous data value between transfers to prevent floating inputs.

SDATA[63:0]#

AMD Athlon Processor System Bus Processor Data Channel

The SDATA[63:0]# transfer data between the processor and system.

As Outputs:

The AMD-762 system controller drives SDATA[63:0]# with each valid data

quadword. SDATA[63:0]# are skew-aligned with the source-synchronous clocks,

SDATAINCLK[3:0]#.

As Inputs:

The AMD-762 system controller samples SDATA[63:0]# and transfers the data

to the memory. The SDATA[63:0]# are sampled by the AMD-762 system controller on

each edge of SDATAOUTCLK[3:0]#.

SDATA[63:0]# are floated out of RESET#. Write data is driven by the processor and read

data is driven by the system controller. The AMD-762 system controller drives the

previous data value between transfers to prevent floating inputs.

SDATAINCLK[3:0]#

AMD Athlon Processor System Bus System Data In Clock

SDATAINCLK[3:0]# is the single-ended source-synchronous clock driven by the AMD-762

system controller to transfer data on SDATA[63:0]# and check bits on SCHECK[7:0]#.

Sixteen bits of data and two check bits are skew-aligned with each clock. Data is

transferred on each clock edge.

These signals are driven inactive (negated) when the CLKFWDRST signal is asserted (true).

When CLKFWDRST is negated, SDATAINCLK[3:0]# run continuously after three clock

delays.

SDATAINVAL#

AMD Athlon Processor System Bus System Data In Valid

SDATAINVAL# is driven by the AMD-762 system controller and controls the flow of data

into the processor. SDATAINVAL# can be used to introduce an arbitrary number of cycles

between quadword pairs (128 bits). SDATAINVAL# is skew-aligned with the source-

synchronous clock, SADDINCLK#.

SDATAOUTCLK[3:0]#

AMD Athlon Processor System Bus System Address Out Clock

SDATAOUTCLK[3:0]# is the single-ended source-synchronous clock driven by the

processor and is used to transfer data and check bits on the SDATA[63:0]# and

SCHECK[7:0]#. Sixteen bits of data and two check bits are skew-aligned with each clock.

Data is transferred on each clock edge.

These signals are driven inactive (negated) when the CLKFWDRST signal is asserted (true).

When CLKFWDRST is negated, SDATAOUTCLK[3:0]# run continuously after three clock

delays.

SYSCLK

AMD Athlon Processor System Bus System Clock

SYSCLK is a single-ended input clock signal provided by the system clock generator to the

phase locked loop (PLL) of the AMD-762 system controller. Frequencies of 66.67 MHz,

100 MHz, or 133.33 MHz are supported.

Table 34.

Signal Descriptions (Continued)

Signal

Type

Description

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