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AMD-762 Datasheet(PDF) 36 Page - Advanced Micro Devices |
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AMD-762 Datasheet(HTML) 36 Page - Advanced Micro Devices |
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36 / 122 page  24 Functional Operation Chapter 2 AMD-762™ System Controller Data Sheet 24416C—December 2001 Preliminary Information The AMD-762 system controller implements three internal PLLs to control clock skew on-chip for the SYSCLK, AGPCLK, and PCICLK domains. An external feedback path is required on the motherboard for the 66-MHz PCI PLL when operating in 66-MHz mode. This requires the PCI_66CLK[0] output pin to be connected back into the AMD-762 system controller’s PCICLK input for skew control, as shown in Figure 7 on page 23. These PLLs can be bypassed for motherboard testing. Refer to Chapter 3 for further details of PLL bypass testing. Figure 8. System Clocking with 33-MHz PCI Bus 100/133 MHz 66 MHz SYSCLK AGPCLK CLKOUT[0]n CLKOUT[1]n CLKOUT[3]n CLKOUT[2]n DDR DIMMs PCICLK 66 MHz AGP Slot 32-bit, 33-MHz PCI Bus Slots 33 MHz 33-MHz PCI Clocks Clock Generator 33 MHz (for Southbridge) AMD-762™ System Controller Northbridge AMD-766™ Peripheral Bus Controller Southbridge |
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