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Signal Descriptions

Chapter 7

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

SYSFILLVALID#

AMD Athlon™ Processor System Bus Fill Valid

This pin is asserted by the AMD-762™ system controller to validate the current memory or

I/O data transfer to the processor. SYSFILLVALID# can be sampled by the CPU during D0

or D1 data phases.

PCI Interface Signals

AD[63:00]

PCI Address/Data Bus

This is the multiplexed address/data bus, sampled on the rising edge of PCICLK. The

address is valid on AD[63:00] during the first clock when FRAME# is asserted. Write data

is valid on AD[63:00] when IRDY# is asserted and read data is valid when TRDY# is

asserted. Data transfers occur on AD[63:00] when both IRDY# and TRDY# are asserted.

Data transfers may be 32 bits or 64 bits based on the REQ64#/ACK64# protocol.

The AD[31:0] pins are also used for initialization pinstrapping to configure various startup

parameters of the AMD-762 system controller. The initialization pinstraps are configured

with a weak pullup or pulldown and sampled by the AMD-762 system controller during

system reset. Refer to the “Initialization Pinstrapping” section at the end of this table for

further details.

C/BE[7:0]#

PCI Command/Byte Enables

During the address phase, these pins define the PCI command. During the data phase

these pins are used as byte enables. The byte enables for the upper 32 bits of data

(C/BE[7:4]) are used only during 64-bit transfers that are determined by the

REQ64#/ACK64# protocol.

These pins are also used for initialization pinstrapping to configure various startup

parameters of the AMD-762 system controller. The initialization pinstraps are configured

with a weak pullup or pulldown and sampled by the AMD-762 system controller during

system reset. Refer to the “Initialization Pinstrapping” section at the end of this table for

further details.

DEVSEL#

STS

PCI Device Select

The AMD-762 system controller asserts this pin when an external bus master drives a valid

address within the AMD-762 system controller’s memory region, as defined by the PCI

Top of Memory register (Dev 0:F0:0x9C). The AMD-762 system controller responds only to

memory cycles. This pin is sampled by the AMD-762 system controller when the CPU

accesses a PCI target.

FRAME#

STS

PCI Cycle Frame

The FRAME# pin is asserted by the AMD-762 system controller to indicate the beginning

of a bus transaction. FRAME# is sampled by the AMD-762 PCI target controller when an

external bus master is performing a transaction on the PCI bus.

GNT[6:0]#

PCI Bus Grant

As the PCI bus arbiter, the AMD-762 system controller asserts one of these device-specific

bus grant signals off the rising clock edge to indicate to an initiator that it has been

granted control of the PCI bus the next time the bus is idle. In 66-MHz PCI mode only,

GNT[2:0]# are used and all other grant pins are unconnected on the motherboard.

GNT[6:0]# signals are never floated. They are negated off the rising edge of the PCICLK

input, indicating that no device has been granted the bus. One of the GNT[6:0]# signals is

asserted off the rising edge of the clock, indicating the particular channel that is granted

use of the bus.

These pins are also optionally used in test modes as described in Table 36 on page 98,

and in Chapter 3.

Table 34.

Signal Descriptions (Continued)

Signal

Type

Description

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