AMD-762 datasheet(48/122 Pages) AMD

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Test

Chapter 3

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

to some I/O cells that cannot be asynchronously forced into a

three-state mode.

Board test mode is entered when the AD[25] pin is asserted

High simultaneous with the TEST# pin during RESET#

assertion. The test mode is then latched coming out of reset.

The AD[09] pin should also be pulled up to force the internal

PLLs to be bypassed.

Three-state mode can be exited by an assertion of the RESET#

pin. This reset also disables the PLL bypass mode if it was

entered.

3.1.1

Board Test Mode Clocking

When entering three-state mode, the PLLs should also be

bypassed as described above. This procedure forces the clocks

driven on the SYSCLK and AGPCLK input pins to be routed

directly to the appropriate clock domains. The SYSCLK and

AGPCLK pins must then be clocked for six clocks as required to

force some AMD-762 system controller I/O pads to the three-

state mode.

3.2

NAND Tree Test Mode

NAND tree testing is used on the tester and can also be used

during board testing to test connectivity of AMD-762 system

controller inputs. In this test mode, each AMD-762 system

controller input can be asserted one pin at a time, and for each

pin assertion there should be a change in state on the output of

the respective NAND tree. The AMD-762 system controller

pr o v ides m u ltipl e NA N D tr ees, whi c h speeds up

characterization of the device, and also reduces motherboard

test time. The AMD-762 system controller NAND trees are

divided by I/O type, which create the following trees:

AMD Athlon system bus NAND tree

This tree includes all signals on the AMD Athlon processor

system bus. SYSCLK is not included in the NAND tree. The

output of this tree is the GNT[0]# pin. The ordering for this

NAND tree is shown in Table 2 on page 38.

AMD-762 Datasheet(PDF) 48 Page - Advanced Micro Devices