AMD-762 datasheet(98/122 Pages) AMD

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Signal Descriptions

Chapter 7

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

REQ[6:0]#

PCI Bus Request

As the PCI bus arbiter, the AMD-762™ system controller samples these device-specific bus

request signals to determine if another agent requires control of the PCI bus. In 66-MHz

PCI mode only, REQ[2:0]# is used and all remaining request signals must be pulled up to

the inactive state.

These signals are sampled by the rising edge of every PCICLK. If active, the arbiter issues

the corresponding GNT[6:0]# when the bus is available.

REQ64#

STS

Request 64

This pin is used to signal that the master requests a 64-bit transfer. The AMD-762 system

controller must assert this signal (Low) during reset (RESET# asserted Low) to signal

64-bit devices that they can operate in 64-bit mode.

ACK64#

STS

Acknowledge 64

This pin is used to signal that the agent is capable of completing a 64-bit transfer.

RESET#

System Reset

Asserting RESET# resets the AMD-762 system controller and sets all register bits to their

default values (except memory controller registers as required for ACPI S3 support).

Bidirectional signals are three-stated and outputs are driven inactive. RESET# is driven by

the PCIRST# output of the AMD-768™ peripheral bus controller or AMD-766™ peripheral

bus controller. See “Pin States at Reset” on page 98.

This signal may be asynchronous to SYSCLK and PCICLK. It is synchronized internally,

therefore it must be active for a minimum of four PCICLK periods.

SERR#

PCI System Error

SERR# is used by the AMD-762 system controller to transfer GART errors, ECC errors, or

AGP A_SERR# pin assertion errors to error reporting logic on the AMD-766 peripheral bus

controller.

STOP#

STS

PCI Stop

As a target, the STOP# signal is asserted by the AMD-762 PCI target logic to initiate a

target disconnect, ending the current transfer. As a master, the AMD-762 system controller

ends the current transfer when it samples the STOP# signal asserted.

TRDY#

STS

PCI Target Ready

TRDY# is asserted by the AMD-762 system controller during accesses of DRAM by an

external bus master when read data is valid or when the target logic is ready to receive

write data. This signal is sampled by the AMD-762 PCI master logic when the AMD-762

system controller is accessing an external PCI target.

This pin is also optionally used in test modes as described in Table 36 on page 98, and in

Chapter 3.

Table 34.

Signal Descriptions (Continued)

Signal

Type

Description

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