AMD-762 datasheet(32/122 Pages) AMD

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Functional Operation

Chapter 2

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

While AGP relieves traffic on the PCI bus and frees up graphics

adapter memory, the greatest impact on system performance

comes from the many innovations AGP brings to data transfer

operations. These improvements include the following:

Split Transactions —Requests to read or write data are

separate from the data transfers.

Pipelined Requests—Requests can be issued contiguously

and stored in the AMD-762 system controller request queue.

Pipelining allows AGP to achieve high levels of concurrency

with PCI and the processor.

Pipeline Grants—Pipelined GNT# signals for up to four

write transactions.

Prioritizing (reordering)—Read and write requests can be

assigned a high priority or a low priority to ensure that

more urgent requests are serviced first.

Defined-Length Requests—The amount of data requested is

indicated in the AGP command, rather than the duration of

an asserted signal, such as FRAME# in PCI.

An 8-byte minimum data size for AGP 2x/4x transfers, which

provides a more efficient method for moving the large

amount of data typical in a graphics request.

A separate, optional Sideband Address (SBA) bus that

enables concurrent transmissions of requests and data

transfers.

Optional 2x/4x modes that increase the AGP graphics

adapter data transfer rate.

Freedom from the coherency requirements of PCI, which

eliminates the latency resulting from cache snooping.

Full PCI 2.2 capability, which enables the AMD-762 system

controller to pass programming information from the

processor to the graphics adapter.

A Graphics Address Remapping Table (GART).

The AGP request queue is split up into two queues — one for

read requests and one for write requests. Because there is a

reordering FIFO in the address module, the request queues do

not have to be large. The read queue is big enough to hold all

outstanding read requests, which avoids stalling writes that

run on the bus while the reads occur to memory.

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