AMD-762 datasheet(69/122 Pages) AMD

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Chapter 4

Electrical Data

24416C—December 2001

AMD-762™ System Controller Data Sheet

Preliminary Information

Figure 15.

DDR Clock Specifications

Table 21 shows the AMD-762 system controller preliminary

timing information.

DDR Write Timing

Figure 16 on page 58 shows a DDR interface output block

diagram. Figure 17 on page 59 shows basic AC timing for DDR

write cycles.

Note: All information shown under DDR Write Timing is preliminary.

tCKlo

tCKhi

CLKOUTH[5:0]

CLKOUTL[5:0]#

Table 21.

AMD-762™ System Controller Preliminary DDR Timing Information*

Symbol

Parameter Description

Min

Max

Unit

Figure

VIL (AC)

AC Input Low Voltage

VREF – 0.35

VIH (AC)

AC Input High Voltage

VREF + 0.35

tADsu

ADDR/CMD Setup to CK

7.5

8.5

Figure 17

on page 59

tADhld

ADDR/CMD Hold from CK

2.5

3.6

tDQsu

DQ/DM Setup to DQS

2.4

2.5

tDQhld

DQ/DM Hold from DQS

2.4

2.6

tWPREsu

Write Preamble Setup

2.8

3.4

tWPREhld

Write Preamble Hold

5.1

5.8

tWpostA

Write Postamble

4.5

5.0

tDSsu

DQS Falling Edge to Next CK Rising Edge

5.2

5.6

tDQSdly

Write Command to First DQS Latching Transition

9.0

9.9

Notes:

* This table contains preliminary information, which is subject to change. Timing reference load (applied to all chip-level outputs) used for all

information contained herein is a 30-pF capacitance. A CAS latency of 2.5 is used unless otherwise indicated.

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