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Electrical Data

Chapter 4

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

Table 14.

AGP 2x and 4x Mode DC Specifications*

DC Specifications for 2x Mode Only at 3.3-Volt Signalling

Symbol

Parameter Description

Condition

Min

Max

Units

Notes

VREF

Input Reference Voltage

0.39 VDDQ

0.41 VDDQ

V1, 2

IREF

VREF Pin Input Current

0 < VIN < VDDQ

±10

µA2

CIN

Input Pin Capacitance

∆CIN

Strobe to Data Pin Capacitance Delta

–12

3, 4

DC Specifications for 2x or 4x Mode at 1.5-Volt Signalling

Symbol

Parameter Description

Condition

Min

Max

Units

Notes

VREF

Input Reference Voltage

0.48 VDDQ

0.52 VDDQ

V1, 2

IREF

VREF Pin Input Current

0 < VIN < VDDQ

±5

µA2

CIN

Input Pin Capacitance

∆CIN

Strobe to Data Pin Capacitance Delta 2x Mode

4x Mode

–1

3, 4

Notes:

*This table contains preliminary information, which is subject to change.

1. AGP allows differential input receivers to achieve the tighter timing tolerances needed for 133 Mbytes/s. Nominal value of VREF is 0.4

VDDQ for 3.3-V signalling and 0.5-VDDQ for 1.5-V signalling. VREF can be designed with 2% resistors to achieve the specified minimum

and maximum values. The value of VREF is intended to specify the center point of the VIL/VIH range. For the 3.3-V signalling case, at

nominal VDDQ (3.3 V), VREF is 1.32 V ± 2.5%. A single input interface buffer can be designed to meet the VIL/VIH levels of both the

AGP and PCI specifications. As in other AGP specifications, note that the VDDQ references the I/O ring supply voltage and not the

component supply.

2. Although a differential input buffer is not a required implementation, it is recommended especially at higher data transfer rates

where there is less timing margin. All designs regardless of implementation style must meet all other specifications. Component

designs requiring a reference are required to adhere to the VREF and IREF specifications and to facilitate a common reference circuit.

(A common reference circuit is not applicable to add-in card designs, because VREF is not supplied via the connector.)

3. Capacitance specifications refer only to pin capacitance on the AGP-compliant components used on the AGP interface.

4. Delta CIN is required to restrict timing variations resulting from differences in input pin capacitance between the strobe and associ-

ated data pins. This delta only applies between signal groups and their associated strobes: AD_STB1, AD_STB1#=>AD[31::16], and

C/BE[3::2]; AD_STB0, AD_STB0#=>AD[15::00], and C/BE[1::0]#; SB_STB, SB_STB#=>SBA[7::0]. (Complementary strobes apply to

4x mode only.)

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