AMD-762 datasheet(29/122 Pages) AMD

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Chapter 2

Functional Operation

24416C—December 2001

AMD-762™ System Controller Data Sheet

Preliminary Information

asserts its PCI request pin, but the Southbridge is allowed to

complete its transactions before the SBGNT# is deasserted.

Southbridge with an

Integrated PCI-PCI

Bus Bridge

A significant performance benefit of the AMD-762 system

controller is the support of a 66-MHz, 64-bit PCI bus. This

allows the system to support peripherals that consume much

higher bandwidth, but it requires a 66-MHz Southbridge and is

limited to a maximum of two additional PCI slots due to the

tight 66-MHz PCI timing.

In this configuration, an AMD-768™ peripheral bus controller

supports a 66-MHz PCI primary bus, and integrates a PCI to

PCI bridge. The secondary bus of this bridge supports a 32-bit,

33-MHz PCI bus that supports up to seven slots that can be

used for less bandwidth-intensive peripherals. In this system

configuration, the Southbridge connects to the AMD-762

system controller’s REQ[0]# and GNT[0]# request/grant pair,

and the two optional slots on the primary bus connect to the

REQ[2:1]# and GNT[2:1]# pairs. All 32-bit, 33-MHz PCI slots

are arbitrated by the Southbridge and therefore connect their

request/grant pairs to the Southbridge.

Note: Only REQ[2:0]# and GNT[2:0]# should be used when

operating the primary PCI Bus at 66 MHz.

Arbitration Priority

Access priority rotates between the Southbridge (when

connected to the SBGNT# pin) and CPU/PCI bus masters

(GNT[6:0]#) such that the following arbitration sequence could

be seen in a busy system:

1. Southbridge (SBGNT# pin only)

2. CPU

3. Southbridge (SBGNT# pin only)

4. PCI master (one of GNT[6:0]#)

5. Repeat step 1

The SBREQ#/SBGNT# pin should be used only with a legacy

Southbridge such as described in “Legacy Mode—Single PCI

Bus Southbridge” on page 16.

When there are no requests for the bus, ownership can default

to either processor through the AMD-762 system controller or

the last PCI bus master that had bus ownership. This mode is

called bus parking and is controlled by the PCI Arbitration

Control register (Dev 0:F0, 0x84, bit 0).

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