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Chapter 7

Signal Descriptions

24416C—December 2001

AMD-762™ System Controller Data Sheet

Preliminary Information

IRDY#

STS

PCI Initiator Ready

The AMD-762™ system controller asserts this signal during PCI transactions to indicate

that write data is valid or it is ready to receive read data. It is sampled by the AMD-762

system controller during memory transactions by external bus masters to DRAM.

This pin is also optionally used in test modes as described in Table 36 on page 98, and in

Chapter 3.

PAR

PCI Bus Parity

PAR is used to generate and check for even parity across the AD[31:0] and C/BE[3:]# pins.

The AMD-762 system controller generates but does not check parity.

This pin is also optionally used in test modes as described in Table 36 on page 98, and in

Chapter 3.

PAR64

Parity 64

This pin is used to provide the parity bit for the upper 32 bits of data and upper four byte enables.

PCICLK

PCI Clock

PCICLK is a 33.33-MHz clock provided by the system clock generator. It is used by the

AMD-762 system controller logic in the PCI clock domain when operating in 33-MHz

mode only. When operating in 66/33-MHz mode, this pin is used as the feedback clock to

the internal PLL. Refer to Chapter 2 for details on the PCI clocking options in the AMD-762

system controller.

M66EN

66-MHz Enable

This signal indicates that all peripherals on the PCI bus segment support 66-MHz

operation. When Low, this signal indicates that a card is installed that supports only

33-MHz (or below) operation, and the AMD-762 system controller must operate at this

speed instead of 66 MHz.

PCI_66CLK[2:0]

66-MHz PCI Clock Outputs

These clocks are provided to a 66-MHz Southbridge and two 66-MHz PCI slots when

operating in 66/33-MHz PCI mode. When operating in 33-MHz-only mode, these pins are

unused. Note that if the M66EN pin (see above) is deasserted, then these clocks are scaled

back to 33 MHz. Refer to Chapter 2 for details on the PCI clocking options in the AMD-762

system controller.

SBGNT#

PCI Grant to Peripheral Bus Controller

SBGNT# grants control of the PCI bus to the PCI-ISA/IDE bridge functions implemented in

the AMD-768™ peripheral bus controller or AMD-766™ peripheral bus controller.

SBGNT# is driven off the rising edge of PCICLK. RESET# forces SBGNT# inactive. SBGNT#

is asserted in response to a SBREQ#. SBGNT# and GNT[6:0]# all grant control of the bus

to an external device.

SBREQ#

PCI Request from Peripheral Bus Controller

The AMD-762 system controller samples SBREQ# to determine if the AMD-768 or

AMD-766 peripheral bus controller needs PCI bus access.

This signal is sampled by the rising edge of every PCICLK. If asserted, the arbiter issues a

SBGNT# when the bus is available.

Table 34.

Signal Descriptions (Continued)

Signal

Type

Description

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