AMD-762 datasheet(68/122 Pages) AMD

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Electrical Data

Chapter 4

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

Figure 14.

Clock Skew Requirements

4.5.2

DDR Interface Timing

Table 19 and Table 20 show the DDR SDRAM interface

timings. Figure 15 on page 57 shows DDR clock specifications.

The AMD-762 system controller’s DDR DRAM interface complies

to JEDEC specifications for 100/133-MHz device timing.

SYSCLK

AGPCLK

tSkew

1.15 V

0.4 (VDD_PCI)

tSkew

Table 19.

DDR Clock Switching Characteristics for 100-MHz DDR Operation

Symbol

Parameter Description

Preliminary Data

Figure

Comments

Min

Max

Frequency

100 MHz

CLKOUTH/L[5:0] High Time

4.75 ns

CLKOUTH/L[5:0] Low Time

4.75 ns

CLKOUTH/L[5:0] Fall Time

0.86 ns

1.30 ns

Drive strength:

P = 3, N = 2;

PSLEW = 5, NSLEW = 5

CLKOUTH/L[5:0] Rise Time

0.86 ns

1.30 ns

CLKOUTH/L[5:0] Period Stability

± 2%

CLKOUTH/L[5:0] Skew

0.12 ns

Relative to all other

CLKOUTH/L pairs

*This table contains preliminary information, which is subject to change.

Table 20.

DDR Clock Switching Characteristics for 133-MHz DDR Operation

Symbol

Parameter Description

Preliminary Data

Figure

Comments

Min

Max

Frequency

133 MHz

CLKOUTH/L[5:0] High Time

3.625 ns

CLKOUTH/L[5:0] Low Time

3.625 ns

CLKOUTH/L[5:0] Fall Time

0.86 ns

1.30 ns

Drive strength:

P = 3, N = 2;

PSLEW = 5, NSLEW = 5

CLKOUTH/L[5:0] Rise Time

0.86 ns

1.30 ns

CLKOUTH/L[5:0] Period Stability

± 2%

CLKOUTH/L[5:0] Skew

0.12 ns

Relative to all other

CLKOUTH/L pairs

*This table contains preliminary information, which is subject to change.

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