AMD-762 datasheet(34/122 Pages) AMD

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Functional Operation

Chapter 2

AMD-762™ System Controller Data Sheet

24416C—December 2001

Preliminary Information

There are no ordering restrictions between AGP and PCI

transactions on the AGP bus.

PCI transactions on the AGP bus follow the PCI ordering rules

described in the PCI Local Bus Specification, Revision 2.2.

High-priority requests are re-ordered in front of low-priority

requests.

There is no ordering relationship between high-priority

reads, high-priority writes, and any other transfer type, such

as low-priority reads, low-priority writes, PCI reads, or PCI

writes.

If a lo w -pr ior i ty data trans f er is in pro g re ss whe n a

high-priority request is received, the data transfer completes

before the high-priority request is serviced —that is, a request

is not preemptable. A high-priority request supersedes a

low-priority request on a request boundary only.

2.5

System Clocking

The AMD-762 system controller requires the following system

clocks:

SYSCLK, used for clocking the AMD Athlon system busses

and the DDR DRAM interface. This clock is typically either

100 MHz or 133 MHz. This clock is also used to create the

differential DDR DRAM clock outputs (CLKOUT[5:0],

CLKOUT[5:0]#).

AGPCLK, 66 MHz, used for clocking the AGP and PCI

internal logic. This feeds the PCI 66-MHz PLL in 66/33-MHz

PCI mode.

PCICLK, provides a 33-MHz PCI bus clock and is used to

synchronize the PCI bus I/O signals to the 33-MHz PCI

signal domain when operating in 33-MHz-only PCI mode.

There are two different clocking schemes for the PCI bus and

Southbridge as described in the following sections.

66-MHz PCI Bus

The highest performance option supports a 66-MHz primary

PCI bus on the AMD-762 system controller, with a 33-MHz

secondary PCI bus controlled by an AMD-768 peripheral bus

controller’s PCI to PCI bridge. This mode also provides up to

two optional slots for 66-MHz peripherals.

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