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AMD-762 Datasheet(PDF) 82 Page - Advanced Micro Devices

Part # AMD-762
Description  System Controller
PDF  122 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AMD-762 Datasheet(HTML) 82 Page - Advanced Micro Devices

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70
Electrical Data
Chapter 4
AMD-762™ System Controller Data Sheet
24416C—December 2001
Preliminary Information
4.5.4
AMD Athlon™ Processor System Bus Timings
Table 27 shows the AMD Athlon processor system bus timings.
Table 27.
AMD Athlon™ Processor System Bus/AMD-762™ System Controller AC Specification
Group
Symbol
Parameter Description
Minimum
Nominal
Maximum
Units
Notes
TNB-SKEW-
SAMEEDGE
Output skew with respect to
the same clock edge
––
400
ps
1
TNB-SKEW-
DIFFEDGE
Output skew with respect to a
different clock edge
––
1025
ps
1
TNB-SU
Input Data Setup Time
500
––
ps
1, 2
TNB-HD
Input Data Hold Time
800
––
ps
1, 2
TRISE
Signal or Clock Rise Time
1
–
3V/ns
TFALL
Signal or Clock Fall Time
1
–
3V/ns
CDATA
Data Pin Capacitance
4
–
12
pF
CINCLK
Input Clock Capacitance
4
–
12
pF
TNB-SYSCLK-
TO-PAD
SYSCLK to Synchronous Signal
Output at Pad (CONNECT,
CLKFWDRST)
2400
–
4800
ps
4, 5
TNB-SETUP-
TO-SYSCLK
Input Setup Time for
Synchronous Signal to SYSCLK
(PROCRDY)
1500
––
ps
4, 5
TNB-HOLD-FRO
M-SYSCLK
Input Hold Time for
Synchronous Signal to SYSCLK
(PROCRDY)
1200
––
ps
4, 5
Notes:
* This table contains preliminary information, which is subject to change.
1. TNB-SKEW-SAMEEDGE is the maximum skew within a clock-forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to the same clock edge.
TNB-SKEW-DIFFEDGE is the maximum skew within a clock-forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
2. Input SU and HLD times are with respect to the appropriate clock forward group input clock.
3. The synchronous signals include
PROCREADY, CONNECT, and CLKFWDRST.
4. This value is measured with respect to the rising edge of SYSCLKIN.
5. Test load = 25 pF.



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