GD3160 datasheet(17/114 Pages) NXP

17 / 114 page

NXP Semiconductors

GD3160

Advanced IGBT/SiC gate driver

VDD, VCC, VCCREG, VEE in regulation, TJ = –40 °C to +150 °C, unless otherwise specified. All voltages referenced to GND1. Currents are

positive into and negative out of the specified pins.

Symbol

Parameter

Min

Typ

Max

Unit

PWM deadtime, DEADT = '0000',

0.128

0.16

0.329

μs

PWM deadtime, DEADT = '0001'

0.206

0.24

0.411

μs

PWM deadtime, DEADT = '0010'

0.4

0.44

0.617

μs

PWM deadtime, DEADT = '0011'

0.71

0.76

0.947

μs

PWM deadtime, DEADT = '0100'

0.982

1.04

1.235

μs

PWM deadtime, DEADT = '0101'

1.448

1.52

1.729

μs

PWM deadtime, DEADT = '0110'

1.952

2.04

2.265

μs

PWM deadtime, DEADT = '0111'

2.418

2.52

2.759

μs

PWM deadtime, DEADT = '1000'

2.922

3.04

3.295

μs

PWM deadtime, DEADT = '1001'

3.388

3.52

3.789

μs

PWM deadtime, DEADT = '1010'

3.892

4.04

4.325

μs

PWM deadtime, DEADT = '1011'

4.358

4.52

4.819

μs

PWM deadtime, DEADT = '1100'

4.862

5.04

5.355

μs

PWM deadtime, DEADT = '1101'

5.328

5.52

5.849

μs

PWM deadtime, DEADT = '1110'

5.832

6.04

6.385

μs

tMIN_DT

(TIME_2 = 0)

PWM deadtime, DEADT = '1111'

6.298

6.52

6.879

μs

Table 11. Low-voltage digital I/O electrical characteristics...continued

[1]

Pins: FSSTATE, FSENB, PWM, PWMALT, SCLK, CSB, MOSI

[2]

CSB, PWMALT connected to VDD

[3]

Guaranteed by design

[4]

MOSI, SCLK, PWM, FSSTATE, FSENB connected to GND1; FSISO connected to GND2

[5]

Pins: MISO, AOUT, INTA (when RTRPT = 1), I = 3.0 mA

[6]

Pins: INTB, INTA (when RTRPT = 0), I = 10 mA

[7]

Pins: MISO, AOUT, INTA (when RTRPT = 1), I = −2.0 mA

[8]

Pins: PWM, PWMALT

[9]

CLoad = 2 nF, guaranteed by design

[10] TIME_2_is Timer scaling bit of MODE1 register

VDD, VCC, VCCREG, VEE in regulation, TJ = −40 to +150 °C, unless otherwise specified. All voltages referenced to GND1. Currents are

positive into and negative out of the specified pins.

Limit value

Symbol

Parameter

Min

Typ

Max

Unit

fSPI

Frequency of SPI operation

[1] [2]

—

MHz

tlead

Falling edge of CSB to rising edge of SCLK (required setup time)

[2]

—

tlag

Falling edge of SCLK to rising edge of CSB (required setup time)

[2]

—

twh

High time of SCLK

[2]

—

twl

Low time of SCLK

[2]

—

tsu1

MOSI to rising edge of SCLK (required setup time)

[2]

—

MOSI to rising edge of SCLK (required hold time)

[2]

—

tSO(en)

Time from falling edge of CSB to MISO low impedance

[2]

—

tSO(dis)

Time from Rising Edge of CSB to MISO high Impedance

[2]

—

tvalid

Time from falling edge of SCLK to MISO data valid

[3] [2]

—

Table 12. SPI timing

GD3160

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 13 — 6 May 2024

17 / 114

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