GD3160 datasheet(84/114 Pages) NXP

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NXP Semiconductors

GD3160

Advanced IGBT/SiC gate driver

Bit

Logic 0 = masked

Logic 1 = not masked

VSUPOVM

PWMing remains enabled, fault not latched or reported. PWM disabled. GL = 1, AMC = 1 if enabled.

OTSDM

PWMing remains enabled, OTSD fault not latched or

reported. Temp reported in ADCVAL and AOUT.

PWM disabled. GL = 1, AMC = 1 if enabled.

OTWM

PWMing remains enabled, OTW fault not latched or

reported. Temp reported in ADCVAL.

PWM enabled.

CLAMPM

PWMing remains enabled, fault not latched or reported. PWM disabled. GL = 1, AMC = 1 if enabled.

OCM

No mask.

PWM enabled.

Table 50. MSK1 register description...continued

[1]

At power up, a VCCREGUV fault should not be latched or reported. The UV_LATCH bit (in CONFIG1) allows PWMing if the VCCREG supply recovers

from an UV condition. INTB follows fault condition. SPI bit is latched.

11.14.14 RMSK1 register (ADDR = 0x0D)

The RMSK1 register values determine which interrupt pin (either INTB or INTA) an unmasked fault is to be

reported. A value of '0' reports the fault to INTB, and a value of '1' reports the fault to INTA. Recall that for INTA

to be configured as a fault pin, the RTRPT bit must be set accordingly in the MODE2 register.

Rb/

ADDR

[4:0]

DATA9

DATA8

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

CRC

Bit #

[23]

[22:18]

[17]

[16]

[15]

[14]

[13]

[12]

[11]

[10]

[9]

[8]

[7:0]

Name/Value

0/1

0x0D

VCCOVA

VCCREGUVA VSUPOVA

OTSD_ICA

OTSDA

OTWA

CLAMPA

DESATA

SCA

OCA

—

Write locked

in normal

mode

—

yes

—

Default

—

Table 51. RMSK1 register bit readout

Bit

Bit function

Logic 0

Logic 1

VCCOVA

Select INTx pin to report VCCOV fault to

Report fault on INTB [1]

Report fault on INTA

VCCREGUVA

Select INTx pin to report VCCREGUV fault to

Report fault on INTB [1]

Report fault on INTA

VSUPOVA

Select INTx pin to report VSUPOV fault to

Report fault on INTB [1]

Report fault on INTA

OTSD_ICA

Select INTx pin to report OTSD_IC fault to

Report fault on INTB [1]

Report fault on INTA

OTSDA

Select INTx pin to report OTSD fault to

Report fault on INTB

Report fault on INTA [1]

OTWA

Select INTx pin to report OTW fault to

Report fault on INTB [1]

Report fault on INTA

CLAMPA

Select INTx pin to report CLAMP fault to

Report fault on INTB [1]

Report fault on INTA

DESATA

Select INTx pin to report DESAT fault to

Report fault on INTB

Report fault on INTA [1]

SCA

Select INTx pin to report SC fault to

Report fault on INTB

Report fault on INTA [1]

OCA

Select INTx pin to report OC fault to

Report fault on INTB [1]

Report fault on INTA

[1]

Default value

11.14.15 STATUS2 register (ADDR = 0x0E)

The STATUS2 register details fault status. Fault bits are cleared on power up, and if not masked, upon a fault

the corresponding fault bit is set to '1' and latched. Write '1' operations to the STATUS2 register are used to

clear latched faults and return the device to normal functionality.

GD3160

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 13 — 6 May 2024

84 / 114

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