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GD3160 Datasheet(PDF) 42 Page - NXP Semiconductors |
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GD3160 Datasheet(HTML) 42 Page - NXP Semiconductors |
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42 / 114 page ![]() NXP Semiconductors GD3160 Advanced IGBT/SiC gate driver aaa-037315 FSENB LS_IGBT_EN LS_PWM HS_FSSTATE PWM controls IGBT gate (FSSTATE = 0) tMINFSENB0 tMINFSENB0 = 0.5 µs nominal tMINFSENB1 = 6.5 µs nominal tMINFSSTATE = 1.0 µs nominal tMINFSENB1 PWM controls IGBT gate (FSSTATE = 1) Gate turns off if FSSTATE = 0 Gate turns on if FSSTATE = 1 HS_IGBT_EN HS_PWM Turn-off occurs 0.5 µs after FSENB Turn-on occurs 6.5 µs after FSENB FSSTATE commands gate OFF FSSTATE commands gate ON 0 0 Figure 12. FSENB and FSSTATE filtering when entering a Fail-safe state To ensure safe transition into PWM control, the delay time for the FSENB is a function of the state of the PWM pins, as shown in Figure 13. Figure 13 shows the handling of control between FSSTATE and PWM as the system exits the fail-safe state. If PWM or FSSTATE transitions during the delay time between tMINFSENB0 and tMINFSENB1, then transitions during the FSENB filter delay time, the PWM control is prioritized and the device immediately moves to follow PWM control. Normal mandatory deadtime is in effect with PWM pins, ensuring a safe transition. If the requested PWM state matches the current state under FSSTATE control, no additional 6 µs delay is added, and PWM control is assumed immediately after tMINFSENB0 expires (0.5 µs after FSENB rising edge). In this way, PWM control is prioritized to minimize distortion of the PWM control. Mandatory deadtime again ensures safe switching once PWM activity restarts. GD3160 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 6 May 2024 42 / 114 |
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