GD3160 datasheet(44/114 Pages) NXP

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NXP Semiconductors

GD3160

Advanced IGBT/SiC gate driver

Activating the FSISO pin (Logic 1) 3-states the gate, independent of other inputs, and sends INTB low (INTA

operation is unchanged). The delay time from FSISO rising edge to the 3-state is tFSISOMIN.

As a fail-safe control local to the HV domain, FSISO receives the highest priority over all other controls or faults.

For example, when the VCCREG (positive gate supply) or VREF are in undervoltage, a logic high at FSISO

brings the gate tristate.

The logic state of FSISO pin and the gate can be read via the STATUS3 register (3-state will be reported as

OFF), and INTB is Logic 0 when FSISO is Logic 1. If the FSISO pin is enabled via the FSISOEN bit in the

MODE2 register and FSISO is Logic 1, then the gate is 3-state (GH off, GL off) regardless of the FSENB and

FSSTATE settings.

If this feature is not used, the FSISO pin should be connected to GND2 and the FSISOEN bit in the MODE2

11.2.4 SPI pins (CSB, SCLK, MOSI, MISO)

GD3160's SPI pins (CSB, SCLK, MOSI, and MISO) provide configuration and fault/status report capabilities.

They are also used to determine the operating state and obtain detailed fault information. The ADC reports its

output through the SPI. For SPI circuitry details, see Section 11.13.

11.2.5 PWM and PWMALT pins

During normal operation, the PWM pin controls the ON/OFF state of the output stage. The GD3160 is designed

to minimize the turn on and turn off delays, minimize the difference between those delays, and minimize pulse-

width jitter.

The PWMALT pin should be connected to the PWM signal that controls the IGBT in the opposite side of the

half-bridge. It disallows simultaneously turning on both IGBTs and it enforces a minimum deadtime (tMIN_DT)

between the logic edges, as shown in Figure 14.

An internal pulldown resistor at PWM and an internal pullup resistor at PWMALT ensure that the output stage is

OFF when neither pin is actively driven.

PWMALT GATE_en

GATE_en

aaa-024511

PWM

tMIN_DT

tON_DLY_GH

tON_DLY_GL

tON_DLY_GH

tMIN_DT

Figure 14. PWM and PWMALT with deadtime enforcement

If PWMALT goes high while PWM is already high, then the gate turns off immediately, without inserting tmin_DT.

If PWM goes high, while PWMALT is already high, a deadtime fault will be latched. In fact, tmin_DT is only applied

on the falling edge of PWMALT, to ensure that the gate does not go high before the programmable deadtime

tmin_DT expires.

GD3160

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 13 — 6 May 2024

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