GD3160 datasheet(7/114 Pages) NXP

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NXP Semiconductors

GD3160

Advanced IGBT/SiC gate driver

7 Pinning information

7.1 Pinning

GD3160

VCC

CLAMP

DESAT

TSENSEA

FSISO

AMC

ISENSE

VREF

AMUXIN

GND2

VEE

VCCREG

VEE

FSSTATE

AOUT

PWMALT

PWM

INTB

INTA

GND1

FSENB

VSUP

aaa-034956

NC2

VDD

CSB

SCLK

MISO

MOSI

GND1

Figure 3. Pinout diagram

7.2 Pin description

Pin number

Pin name

Pin type

Definition

Comments

Pins 1 to 16 (low-voltage, non-isolated pins)

VSUP

Input/power

Primary power supply

for non-isolated low-

voltage (LV) domain.

Main supply input is compatible with 12 V automotive battery range/transients,

referenced to GND1. VSUP may either be (1) driven by 12V, or (2) tied to

VDD and powered by an external, post-regulated 5 V supply.

NC2

No connect

No connection.

NC2 must be connected to GND1.

VDD

Input-output/

power

Power supply for non-

isolated low-voltage

(LV) logic.

Main supply for logic on LV domain, referenced to GND1. VDD may either be

(1) regulated internally to 3.3 V or 5.0 V from VSUP, or (2) tied to VSUP and

CSB

Input/digital

SPI chip select.

Active low CSB activates SPI link and framing.

5, 16

GND1

Ground 1

Ground for non-

isolated (LV) domain

power and logic.

Redundant GND1 pins provide ground reference for all non-isolated low-

voltage (LV) domain signals. Isolated from all circuitry referenced to GND2.

MOSI

Input/digital

SPI MOSI pin.

Input data for GD3160 SPI. MOSI data latches on rising edge of SCLK, MSB

first. Internal passive pulldown to GND1.

MISO

Output/digital

SPI MISO pin.

Data output for GD3160 SPI. GD3160 outputs MISO on falling edge of SCLK,

MSB first.

SCLK

Input/digital

SPI clock.

GD3160 acknowledges SPI clock only when CSB is low. Internal passive

pulldown to GND1.

INTB

Output/Dgital

Interrupt/Fault status

output.

INTB reports fault with active low (logic 0 reports fault). Internal passive pullup

to VDD.

PWM

Input/digital

PWM control

command for gate

output.

Logic high turns on power device gate. PWM pin is ignored during fail-safe,

configuration, BIST, reset, and most fault modes. Internal passive pull down to

GND1.

PWMALT

Input/digital

Complementary PWM

command for gate

output.

Complementary PWMALT enforces deadtime constraint and prevents

accidental shoot-through condition. Connect to GND1 if unused. Internal

passive pull up to VDD.

AOUT

Output/analog

Duty-cycle encoded

output of isolated ADC.

5.0 V, 3.9 kHz (or multiplexed with 5.6 kHz) readout is configurable by SPI.

Pin left open if unused.

Table 2. Pin definitions

GD3160

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 13 — 6 May 2024

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