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GD3160 Datasheet(PDF) 86 Page - NXP Semiconductors |
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GD3160 Datasheet(HTML) 86 Page - NXP Semiconductors |
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86 / 114 page ![]() NXP Semiconductors GD3160 Advanced IGBT/SiC gate driver Bit Bit function Logic 0 Logic 1 SPIERRM SPI CRC or framing error fault mask. PWMing remains enabled, fault not latched or reported. PWM enabled. CONFCRCERRM LV or HV domain CONF register CRC error mask. PWMing remains enabled, fault not latched or reported. PWM disabled. GL = 1, AMC = 1 if enabled. RTMON_FLTM RTMON error mask. PWMing remains enabled, fault not latched or reported. PWM disabled. GL = 1, AMC = 1 if enabled. WDOG_FLTM [1] Watchdog fault mask. PWMing remains enabled, fault not latched or reported, periodic REQADC continues. PWM disabled. GL = 1, AMC = 1 if enabled. COMERRM Internal communications fault mask. PWMing remains enabled, fault not latched or reported. PWM disabled. GL = 1, AMC = 1 if enabled. VEE_OORM VEE out of range fault mask. PWMing remains enabled, fault not latched or reported. PWM disabled. GL = 1, AMC = 1 if enabled. Table 55. MSK2 register description...continued [1] WDOG_FLT indicates LV domain received NO message in response to one of the periodic LV domain DATA messages. This bit should be used only for debug purposes. This bit defaults to "unmasked" at power up. 11.14.17 RMSK2 register (ADDR = 0x10) The RMSK2 register values determine which interrupt pin (either INTB or INTA) an unmasked fault is to be reported. Not all STATUS2 faults can be reported at INTA (such as BIST_FAIL, VDD_UVOV, and so on.). A value of '0' reports the fault to INTB, and a value of '1' reports the fault to INTA. Recall that for INTA to be configured as a fault pin, the RTRPT bit must be set accordingly in the MODE2 register. Rb/W ADDR [4:0] DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 CRC Bit # [23] [22:18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7:0] Name/Value 0/1 0x10 — — DTFLTA — — — — — VREF_UVA VEE_OORA — Write locked in normal mode — — — — yes — — — — — yes yes — Default — — 0 0 0 0 0 0 0 0 1 0 — Table 56. RMSK2 register bit readout GD3160 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 13 — 6 May 2024 86 / 114 |
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