GD3160 datasheet(33/114 Pages) NXP

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NXP Semiconductors

GD3160

Advanced IGBT/SiC gate driver

11.1.4 OV and UV threshold description

The GD3160 has overvoltage and undervoltage monitoring for its key power supplies: VSUP, VDD, VCC,

VCCREG, and VREF. The exception to this rule is that VCCREG has no overvoltage monitoring because the

VCC overvoltage circuit provides that protection. Some of the undervoltage or overvoltage circuits are used to

control internal signals and do not create faults. For example, the VSUP undervoltage circuit does not create a

fault; it is used to enable/disable the VDD regulator.

The over and undervoltage threshold specifications are defined in Figure 5.

aaa-028764

VCCREGUV_TH_HYS

VCCREGUV_TH_L

VVCCREG

under voltage

condition

over voltage

condition

VCCOV_TH_HYS

VCCOV_TH_H

VVCC

Figure 5. Definitions of over and undervoltage hysteresis

If VVCC exceeds VCCOV_TH, the IGBT is latched off, and the fault bit is latched and reported via SPI and the

INTA/INTB pins. LV/HV domain communications continue to run.

11.1.5 Power supply sequencing of the low-voltage domain

When voltage is applied to the VSUP (or VSUP/VDD if the pins are connected) at power up, internal logic

supplies of the low-voltage domain turn on with the rise of VSUP. Once VSUP exceeds VSUPUV_TH, the VDD

regulator is enabled.

When VDD exceeds VDDUV_TH, the low-voltage domain begins periodically sending a REQADC command

(Request ADC) and monitoring the high-voltage domain's response. When the low-voltage domain receives a

valid response from the high-voltage domain's, the low-voltage domain enters Normal mode state and is able to

PWM the IGBT.

The power-up timing diagrams of the low-voltage domain are shown below. The two configurations shown are

with and without the VSUP and VDD pins connected on the circuit board.

GD3160

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 13 — 6 May 2024

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GD3160 Datasheet(PDF) 33 Page - NXP Semiconductors