GD3160 datasheet(96/114 Pages) NXP

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NXP Semiconductors

GD3160

Advanced IGBT/SiC gate driver

12 Operation

Get the GD3160 up and running in an application using the steps given in this section:

1. Power up the GD3160 safely into a zero-fault state per Section 12.1.

2. Run BIST upon initialization per Section 12.2.

• If BIST is run on power down, skip this step.

3. The GD3160 now may be safely used in the default configuration now, as detailed in Section 12.3.

4. Configure the GD3160 for an application using SPI and return to normal operation, according to

Section 12.4.

5. Exceptions to normal operation are given by fault reactions described in Section 12.5.

6. Manage the system safe state with fail-safe controls and modes given to Section 12.6.

12.1 GD3160 power-up sequence

The following sequence can be used as a guideline for powering up the GD3160.

1. Bring up VSUP/VDD to power up the LV domain properly. Passive pullup/pulldown on input pins ensure a

safe state.

2. Configure all MCU I/O connected to the GD3160.

a. Set CSB, FSENB = Logic 1.

b. Set MOSI, PWM, FSSTATE = Logic 0.

c. Set MCU pins seeing GD3160’s INTB, INTA, and AOUT pins to be inputs.

3. Confirm LV domain is working properly without faults, while HV domain is still unpowered.

a. Verify the following to confirm GD3160 is in the right state (WAIT state) and working properly:

i. INTB = Logic 0

ii. AOUT duty cycle is d = 5 % (before HV domain is powered up)

iii. AOUT period is 4 kHz ±3 % (verifies GD3160 internal clock)

b. Read SPI registers to ensure no faults on LV domain:

i. Check STATUS2 register to ensure VDD is properly powered up (no VDD_UVOV fault) and that

there are no errors in SPI communication (no SPIERR fault).

ii. Check for LV die OTSD_IC fault by reading STATUS1

iii. A watchdog fault (WDOG_FLT) is acceptable at this point, since we have not powered the HV

domain, the LV/HV domain communications will not yet work.

c. Confirm correct pin states on LV domain I/O pins:

• Read STATUS3 register to confirm PWM, PWMALT, FSENB, FSSTATE, and INTB pins are in the

correct states.

4. Enable the DC-DC converter that powers the HV domain (VCC) to complete the power-up sequence, and

clear/diagnose any faults upon completing power up.

a. Enable the power supply supplying VCC, and wait for the supply/regulators to stabilize.

b. Output pins indicate when HV domain is powered and working properly (GD3160 is in NORMAL mode):

i. AOUT reports the voltage on TSENSEA, duty cycle is between 10 % and 90 % (no longer reporting

5 %).

ii. INTB = Logic 1 indicates there are no faults present.

iii. If INTB = 0 still at this step, there are faults to clear.

c. Read SPI status registers to ensure no faults persist after full power up. INTB = 1 indicates there are no

faults or all faults were cleared.

i. Check STATUS2 register and clear any latched watchdog faults (WDOG_FLT) remaining from

power up.

GD3160

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Product data sheet

Rev. 13 — 6 May 2024

96 / 114

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