GD3160 datasheet(97/114 Pages) NXP

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NXP Semiconductors

GD3160

Advanced IGBT/SiC gate driver

ii. Check STATUS1 register for any fault with incorrect gate supply (no VCCOV or VCCREGUV faults),

load (no DESAT, etc.) or temperature element (no OTSD or OTW faults) and clear as needed.

iii. A REQADC command of the TSENSEA should confirm the reading seen on AOUT.

d. Confirm correct expected states on HV domain connections:

• Read STATUS3 register to ensure FSISO and power device gate (VGE) are in the expected state.

The GD3160 is now ready for BIST, configuration, or operation with default settings.

12.2 Perform BIST upon initialization

Upon initial configuration, perform a BIST with the relevant GD3160 settings configured.

1. If not already done, enter Configuration mode by writing a '1' to the CONFIG_EN bit in the MODE2 register.

2. Configure protections for BIST to check.

a. If operating in a system with a negative gate voltage, set the VEE_OORM mask bit (in MSK2 register)

to 1 so that BIST checks the comparator monitoring for VEE out of range (OOR) Failure mode. Even if

VEE_OORM will be masked in the application, this is one setting the BIST looks at to determine what to

check. The VEE_OORM mask bit can be set later to any value.

b. If operating a system without a negative gate voltage (minimum gate-emitter voltage = 0 V),

VEE_OORM may be left at 0, the default value.

3. Write a 1 to the BIST bit in the MODE2 register. This initializes the BIST process. See Section 11.16 for

additional information.

4. Following BIST completion, write BIST = 0 to end the BIST mode and deliver the result to the INTB pin.

• For block-level elaboration on the BIST result, send a REQBIST command and view the response. See

Section 11.16 for additional information.

5. Because PWM is disabled by configuration mode (CONFIG_EN = 1), after passing BIST the MCU can verify

the system path to various pins, if not already done.

a. Verify paths to input pins PWM, PWMALT, FSSTATE, FSENB, and FSISO pins by toggling the state

from the MCU and reading pin state (as seen by the GD3160) back over STATUS3 register.

b. The INTA and INTB output states can also be verified by STATUS3, the MCU can compare its own pin

state to the state reported by the GD3160 STATUS3 bit state. This can be done during a BIST fail or

pass state.

6. Write desired fault mask settings back to all mask registers (MSK1, MSK2, RMSK1, RMSK2) per application

settings. This enables desired fault and protections reporting now that BIST has been completed with as

many circuits as desired active.

7. At this point, BIST and verification measures are complete. There are two ways to proceed:

a. Write CONFIG_EN = 0 to leave CONFIG mode and enable PWMing with default settings. Continue to

Section 12.3.

b. Leave CONFIG_EN = 1 for now to continue configuring the device. Bearing the default configuration in

mind, skip to Section 12.5 for configure the G3160 best for an application.

8. Clear bits POR_1 and POR_2 in STATUS 3 register.

GD3160

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Product data sheet

Rev. 13 — 6 May 2024

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