GD3160 datasheet(72/114 Pages) NXP

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NXP Semiconductors

GD3160

Advanced IGBT/SiC gate driver

The registers that are protected are the CONFIG1 to 7 registers, the MODE1 and 2 registers, the RMSK1

and RMSK2 registers, and the MSK1 and 2 registers, except for VCCREG, SEGDRV_TH and SEGDRVDLY

settings. The GD3160 must be in Configuration mode (CONFIG_EN bit in the MODE2 register = Logic 1) to

alter these registers.

A CRC of all the protected registers is calculated every watchdog cycle. This value is compared to a CRC

that was calculated when the IC exited Configuration mode, including when the CONFIGAOUT, OT_TH, or

OTW_TH registers were updated. A discrepancy between the two CRCs triggers a CONFIGCRCERR and is

reported at the INTB pin and in the STATUS 2 register.

11.13.4 Clearing fault bits

There are several ways to clear a fault bit (contained in the STATUS1 and STATUS2 registers) on GD3160.

Clearing a fault does not require reading the register beforehand.

1. Writing a Logic 1 to the faulted bit in the STATUS1 or STATUS2 register. Writing a Logic 1 to the faulted bit

will clear the faulted bit if the fault is no longer present. This procedure clears the BIST_FAIL , POR_1, and

POR_2 bits, if set. This is the most common method of clearing a fault.

2. Reset the GD3160 logic by toggling the RESET bit in the MODE2 register. Logic 1 at the RESET bit not only

resets the SPI fault bits, it also returns all the low-voltage and high-voltage domains configurable registers to

their default values. When Logic 0 is written, the fault bit(s) will be Logic 0 unless the fault is still present.

3. Conduct BIST test by toggling the BIST bit in the MODE2 register. Logic 1 at this bit forces the low-voltage

and high-voltage domains to conduct a BIST. Upon exiting BIST, the low-voltage and high-voltage domain's

logic will be reset to the default state. The only exception is that the BIST procedure will not clear the

BIST_FAIL bit, if that happens to be set.

4. All SPI registers, including fault bits, will be reset to their default values at power up or upon a POR of the

low-voltage domain logic supply.

Exceptions for VDD undervoltage:

• To avoid reporting spurious faults at power up, the GD3160 latches no faults until VDD is in regulation. If a

VDD_UVOV fault is detected, the VDD supply may have fallen to a level that triggers a logic POR. The MCU

can respond by assuming a POR has occurred and reinitialize the GD3160 or it can read a programmed

Exception when HV domain remains powered:

• When VDD falls below VDDUV_TH, the low-voltage domain no longer sends messages to the high-voltage

domain. The high-voltage domain detects a loss communication and reverts to its fail-safe mode. When VDD

returns to a regulated state, the high-voltage domain may have residual latched faults.

11.13.5 Daisy chain operation

Daisy chain operation reduces the total MCU pin count for SPI and increases message length and polling times.

The recommended implementation for inverter applications requiring functional safety is to have two parallel

chains of three devices: one daisy chain for three high-side gate drivers, one daisy chain for three low-side gate

drivers).

All GD3160 in each group have a single CSB connection. The MCU's MOSI pin is connected to the MOSI pin

of the first GD3160 in the chain. The MISO pin of the first GD3160 is connected to the MOSI pin of the 2nd

GD3160, and so on. An example implementation is shown in Figure 38.

Data from the MCU is clocked through the daisy chain to each device while the CSB bit is commanded low

by the MCU. During each SCLK clock cycle, output status from the daisy chain is transferred to the MCU via

the MISO line. On the rising edge of CSB, data stored in the input registers is latched within each GD3160. An

example implementation is shown in Figure 39.

GD3160

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 13 — 6 May 2024

72 / 114

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