GD3160 datasheet(76/114 Pages) NXP

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NXP Semiconductors

GD3160

Advanced IGBT/SiC gate driver

Bit

Bit function

Logic 0

Logic 1

external resistor network to bias from

VREF)

BIST

BIST enable/disable

BIST feature is not active [1]

Requests BIST of LV and HV die. PWMing is disabled

until BIST is complete and BIST is reset to Logic 0. IGBT

is OFF during BIST.

CONFIG_EN

SPI register configuration enable/

disable

Configuration of SPI registers is

disabled. Normal operation.[1]

Enables Configuration of the SPI registers. IGBT gate

is OFF during Configuration. CRC value of configured

registers is calculated and stored on CSB rising edge

when exiting configuration. PWMing is allowed on the

next PWM rising edge after bit = 0. INTB pin reports faults

normally.

RESET

Reset enable/disable

GD31SiC not in Reset. Normal operating

mode. [1]

GD31SiC in reset. All configuration registers are set to

default values. PWMing is disabled. Configuration is

disabled. IGBT Is OFF. INTB = 0.

Table 29. Mode2 register description...continued

[1]

Default value

11.14.3 CONFIG1 register (ADDR = 0x02)

The CONFIG1 register contains ranges for overcurrent (voltage) threshold level, overcurrent filter time, gate

supply undervoltage threshold level, and selects behavior following a gate supply undervoltage event (latching

or non-latching turn-off).

Rb/W

ADDR

[4:0]

DATA9

DATA8

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

CRC

Bit #

[23]

[22:18]

[17]

[16]

[15]

[14]

[13]

[12]

[11]

[10]

[9]

[8]

[7:0]

Name/Value

0/1

0x02

UV_

LATCH

UV_TH [2] UV_TH [1] UV_TH [0]

OCTH [2]

OCTH [1]

OCTH [0] OCFILT [2] OCFILT [1] OCFILT [0]

—

Write locked

in normal

mode

—

yes

—

Default

—

Table 30. CONFIG1 register bit readout

Bit

Bit function

Logic 0

Logic 1

UV_LATCH

Configure VCCREG undervoltage

behavior

PWM is gated by VCCREG undervoltage condition,

but not latched off. INTA or INTB follows the

VCCREG UV condition. VCCREG_UV SPI fault

bit is latched. PWM disabled during VCCREG UV

condition only. PWM is allowed upon VCCREG

recovery. [1]

PWM is latched off upon VCCREG undervoltage

condition, until fault is cleared.

INTA or INTB follows the VCCREG UV fault.

SPI fault bit is latched. PWM is disabled until the

VCCREG_UV fault bit is cleared.

Table 31. CONFIG1 bit description

[1]

Default value

Bit value

[2:0]

VCCREG undervoltage threshold

UV_TH[2:0]

Overcurrent fault detection threshold

OCTH[2:0]

Overcurrent fault detection filter time

OCFILT[2:0]

0x00

10.0 V

0.25 V

0.5 µs

0x01

10.5 V

0.50 V

1.0 µs

0x02

11.0 V

0.75 V

1.5 µs

0x03

11.5 V [1]

1.00 V [1]

2.0 µs [1]

0x04

12.0 V

1.25 V

2.5 µs

0x05

12.5 V

1.50 V

3.0 µs

Table 32. CONFIG1 parameter ranges

GD3160

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 13 — 6 May 2024

76 / 114

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