PM7346 datasheet(235/419 Pages) PMC

235 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 214

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

FULL

Bit 5

BLFILL

Bit 4

Unused

Bit 3

FULLI

Bit 2

OVRI

Bit 1

UDRI

Bit 0

LFILLI

Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR

Clear, and TDPR Transmit Data register and reads of the TDPR Interrupt

Status/UDR Clear register should not occur at rates greater than 1/8th that of the

clock selected by the LINESYSCLK bit of the S/UNI-QJET Misc. register (09BH,

19BH, 29BH, 39BH).

LFILLI:

The LFILLI bit will transition to logic 1 when the TDPR FIFO level transitions

to empty or falls below the value of LINT[6:0] programmed in the TDPR Lower

Interrupt Threshold register. LFILLI will assert INTB if it is a logic 1 and

LFILLE is programmed to logic 1. LFILLI is cleared when this register is read.

UDRI:

The UDRI bit will transition to 1 when the TDPR FIFO underruns. That is, the

TDPR was in the process of transmitting a packet when it ran out of data to

transmit. UDRI will assert INTB if it is a logic 1 and UDRE is programmed to

logic 1. UDRI is cleared when this register is read.

OVRI:

The OVRI bit will transition to 1 when the TDPR FIFO overruns. That is, the

TDPR FIFO was already full when another data byte was written to the TDPR

Transmit Data register. OVRI will assert INTB if it is a logic 1 and OVRE is

programmed to logic 1. OVRI is cleared when this register is read.

PM7346 Datasheet(PDF) 235 Page - PMC-Sierra, Inc

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