TMPR3916 datasheet(129/225 Pages) TOSHIBA

129 / 225 page

Chapter 7 CAN Module (TXCAN)

Preliminary

7-8

Transmission Request Reset Register (TRR)

Bit

Name



TRR

Bit

Name

Function

Reset

Value

Mode



Wired to zero

14:0

TRR

Setting TRRn causes a transmission request to be cancelled that

was initiated by the corresponding bit TRSn, provided that the

transmission of this mailbox is not currently in process. If the

corresponding message is currently processed the bit will be reset in

the following cases: a successful transmission (normal operation),

an aborted transmission in case of a lost arbitration or an error

condition detected on the CAN bus line. In case of an aborted

transmission, the corresponding status bit AAn will be set and in

case of a successful transmission, the status bit TAn will be set.

The bits in TRR will be set by writing a “1” from the MCU. Writing a

“0” has no effect. After power-up, all bits are cleared.

R/S

These bits can only be set by the MCU and reset by the internal logic. They will be reset by internal

logic in case of a successful transmission or an aborted transmission. Bit 15 is not implemented because

the mailbox 15 is the receive-only mailbox. If TRRn is set the write access to the corresponding

mailbox is denied. If a mailbox is configured as receive the corresponding bit in TRR cannot be set by

MCU.

Note:

When TRSn is set, after setting TRRn to “1”:

•

A transmission request of a message, which is not currently in process, will be cleared immediately

(TRSn

→ 0, TRRn → 0, AAn → 1).

•

A transmission request of a message which is currently processed will be cleared in case of a lost

arbitration or an error condition on the CAN bus

(TRSn

→ 0, TRR → 0, AAn → 1).

•

A transmission request of a message which is currently processed will not be cleared if there is no

lost arbitration and no error condition on the CAN bus

(TRSn

→ 0, TRRn → 0, TAn → 1).

Transmission Acknowledge Register (TA)

Bit

Name



Bit

Name

Function

Reset

Value

Mode



Wired to zero

14:0

If the message of mailbox “n” has been transmitted successfully, the

bit “n” of this register will be set and a transmission successful

interrupt is generated, if it is enabled.

The bits in TA will be reset by writing a “1” from the MCU to TA or

TRS. Writing a “0” has no effect. After power-up, all bits are cleared.

R/C

TMPR3916 Datasheet(PDF) 129 Page - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 129 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL